Central Processing Unit Ontology

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FLOW ALGEBRA — CENTRAL PROCESSING UNIT ONTOLOGY
Semantic Library
Version: 4.0
Canonical Page:
https://kirethresearch.org/booksai-core/ontologies/computing-ontologies/computer-architecture/central-processing-unit-ontology.html

FLOW CENTRAL_PROCESSING_UNIT_ONTOLOGY {

  META {
    DOMAIN = "Computing Ontologies"
    SUBDOMAIN = "Computer Architecture"
    ONTOLOGY = "Central Processing Unit Ontology"
    PURPOSE = "Formalise CPU components, instruction execution, processor state, control flow, data paths, memory interactions and performance relationships."
    LOCALE = "en-GB"
  }

  ENTITY_TYPES {
    CENTRAL_PROCESSING_UNIT
    CPU
    PROCESSOR
    CORE
    CONTROL_UNIT
    ARITHMETIC_LOGIC_UNIT
    EXECUTION_UNIT
    INTEGER_UNIT
    FLOATING_POINT_UNIT
    VECTOR_UNIT
    BRANCH_UNIT
    LOAD_STORE_UNIT
    REGISTER
    REGISTER_FILE
    PROGRAM_COUNTER
    INSTRUCTION_REGISTER
    STATUS_REGISTER
    CACHE
    L1_CACHE
    L2_CACHE
    L3_CACHE
    CLOCK
    CLOCK_CYCLE
    PIPELINE
    PIPELINE_STAGE
    FETCH_STAGE
    DECODE_STAGE
    EXECUTE_STAGE
    MEMORY_STAGE
    WRITEBACK_STAGE
    INSTRUCTION
    OPCODE
    OPERAND
    INSTRUCTION_SET
    ISA
    MICROARCHITECTURE
    ADDRESS
    DATA
    MEMORY_REQUEST
    INTERRUPT
    EXCEPTION
    BRANCH
    PREDICTION
    PROCESS
    THREAD
    STATE
    EVENT
    RESOURCE
    CONFIGURATION
    VERSION
    LATENCY
    THROUGHPUT
    CLOCK_RATE
    POWER
    TEMPERATURE
    PERFORMANCE_METRIC
    ERROR
    EVIDENCE
    CONFIDENCE_SCORE
    PROVENANCE_RECORD
  }

  RELATIONSHIPS {
    IS_A
    INSTANCE_OF
    PART_OF
    CONTAINS
    HAS_CORE
    HAS_UNIT
    HAS_REGISTER
    HAS_CACHE
    HAS_PIPELINE
    HAS_PIPELINE_STAGE
    IMPLEMENTS
    EXECUTES
    FETCHES
    DECODES
    READS
    WRITES
    LOADS
    STORES
    COMPUTES
    BRANCHES_TO
    PREDICTS
    CLOCKS
    INTERRUPTS
    RAISES_EXCEPTION
    HAS_INSTRUCTION_SET
    HAS_MICROARCHITECTURE
    HAS_ADDRESS
    HAS_STATE
    TRANSITIONS_TO
    HAS_CLOCK_RATE
    HAS_LATENCY
    HAS_THROUGHPUT
    HAS_POWER
    HAS_TEMPERATURE
    HAS_CONFIGURATION
    HAS_VERSION
    DEPENDS_ON
    PRECEDES
    FOLLOWS
    DERIVED_FROM
    INFERRED_FROM
    HAS_EVIDENCE
    HAS_CONFIDENCE
    HAS_PROVENANCE
    MAPS_TO
    SEMANTICALLY_EQUIVALENT_TO
  }

  INPUTS {
    CPU_SPECIFICATIONS
    ISA_DEFINITIONS
    MICROARCHITECTURE_DEFINITIONS
    REGISTER_DEFINITIONS
    PIPELINE_DEFINITIONS
    CACHE_CONFIGURATIONS
    CLOCK_PARAMETERS
    INSTRUCTION_STREAMS
    EXECUTION_TRACES
    INTERRUPT_RECORDS
    EXCEPTION_RECORDS
    PERFORMANCE_COUNTERS
    POWER_METRICS
    TEMPERATURE_METRICS
    CONFIGURATION_DATA
    VERSION_DATA
    ONTOLOGY_TERMS
  }

  NORMALISE {
    STANDARDISE_CPU_IDENTIFIERS
    NORMALISE_PROCESSOR_NAMES
    NORMALISE_ISA_NAMES
    NORMALISE_REGISTER_NAMES
    NORMALISE_CACHE_UNITS
    NORMALISE_CLOCK_UNITS
    NORMALISE_PERFORMANCE_METRICS
    NORMALISE_POWER_UNITS
    NORMALISE_TEMPERATURE_UNITS
    NORMALISE_VERSION_IDENTIFIERS
    RESOLVE_COMPONENT_IDENTITIES
    ALIGN_ONTOLOGY_TERMS
    REMOVE_DUPLICATES
    VALIDATE_METADATA
    PRESERVE_PROVENANCE
  }

  PROCESS CPU_EXECUTION_PIPELINE {
    INSTRUCTION_STREAM
      -> FETCH
      -> DECODE
      -> OPERAND_RESOLUTION
      -> EXECUTE
      -> MEMORY_ACCESS_IF_REQUIRED
      -> WRITEBACK
      -> ARCHITECTURAL_STATE_UPDATE
  }

  PROCESS FETCH_REASONING {
    PROGRAM_COUNTER
      -> INSTRUCTION_ADDRESS

    INSTRUCTION_ADDRESS
      -> INSTRUCTION_CACHE_LOOKUP

    INSTRUCTION_CACHE_LOOKUP
      -> INSTRUCTION

    INSTRUCTION
      -> INSTRUCTION_REGISTER

    INSTRUCTION_REGISTER
      -> PROGRAM_COUNTER_UPDATE
  }

  PROCESS DECODE_REASONING {
    INSTRUCTION
      -> OPCODE_EXTRACTION

    OPCODE_EXTRACTION
      -> INSTRUCTION_CLASSIFICATION

    INSTRUCTION_CLASSIFICATION
      -> OPERAND_IDENTIFICATION
      -> EXECUTION_UNIT_SELECTION
      -> CONTROL_SIGNAL_GENERATION
  }

  PROCESS EXECUTION_REASONING {
    OPERANDS + EXECUTION_UNIT + OPERATION
      -> COMPUTATION

    COMPUTATION
      -> RESULT

    RESULT
      -> FLAGS_OR_STATUS_UPDATE
      -> WRITEBACK_OR_MEMORY_OPERATION
  }

  PROCESS PIPELINE_REASONING {
    MULTIPLE_INSTRUCTIONS
      -> CONCURRENT_PIPELINE_STATE

    CONCURRENT_PIPELINE_STATE
      -> DATA_HAZARD_CHECK
      -> CONTROL_HAZARD_CHECK
      -> STRUCTURAL_HAZARD_CHECK

    HAZARD
      -> FORWARD_OR_STALL_OR_FLUSH

    RESOLVED_PIPELINE
      -> NEXT_PIPELINE_STATE
  }

  PROCESS BRANCH_REASONING {
    BRANCH_INSTRUCTION
      -> BRANCH_PREDICTION

    BRANCH_PREDICTION
      -> SPECULATIVE_PATH

    ACTUAL_BRANCH_RESULT
      -> PREDICTION_CHECK

    CORRECT_PREDICTION
      -> CONTINUE

    INCORRECT_PREDICTION
      -> PIPELINE_FLUSH
      -> CORRECT_PATH_FETCH
  }

  PROCESS CACHE_REASONING {
    MEMORY_REQUEST
      -> CACHE_LOOKUP

    CACHE_LOOKUP
      -> CACHE_HIT_OR_MISS

    CACHE_HIT
      -> DATA_RETURN

    CACHE_MISS
      -> LOWER_CACHE_OR_MEMORY_REQUEST

    DATA_RETURN
      -> CACHE_UPDATE_IF_REQUIRED
      -> CPU
  }

  PROCESS INTERRUPT_AND_EXCEPTION_REASONING {
    INTERRUPT_OR_EXCEPTION
      -> SAVE_PROCESSOR_CONTEXT

    SAVE_PROCESSOR_CONTEXT
      -> HANDLER_LOOKUP

    HANDLER_LOOKUP
      -> HANDLER_EXECUTION

    HANDLER_EXECUTION
      -> RESTORE_OR_UPDATE_CONTEXT

    RESTORE_OR_UPDATE_CONTEXT
      -> RESUME_OR_TERMINATE
  }

  PROCESS PERFORMANCE_REASONING {
    CPU + WORKLOAD + CONFIGURATION
      -> EXECUTION_PROFILE

    EXECUTION_PROFILE
      -> INSTRUCTIONS_PER_CYCLE
      -> CACHE_BEHAVIOUR
      -> BRANCH_BEHAVIOUR
      -> PIPELINE_BEHAVIOUR
      -> LATENCY
      -> THROUGHPUT
      -> POWER_AND_THERMAL_PROFILE

    EXECUTION_PROFILE
      -> BOTTLENECK_HYPOTHESIS
  }

  RULES {
    IF ENTITY == CPU
    THEN REQUIRE {
      INSTRUCTION_SET
      REGISTER_MODEL
      EXECUTION_MODEL
      MEMORY_INTERFACE
    }

    IF INSTRUCTION EXECUTES
    THEN LINK {
      INSTRUCTION
      OPERANDS
      EXECUTION_UNIT
      CPU_STATE_BEFORE
      CPU_STATE_AFTER
    }

    IF BRANCH_PREDICTION_IS_USED
    THEN DISTINGUISH PREDICTED_PATH FROM COMMITTED_PATH

    IF CACHE_HIT_OCCURS
    THEN PRESERVE CACHE_LEVEL_AND_ACCESS_CONTEXT

    IF EXCEPTION_OCCURS
    THEN PRESERVE {
      EXCEPTION_TYPE
      INSTRUCTION_CONTEXT
      CPU_STATE
      HANDLER_CONTEXT
    }

    IF TWO_CPUS_IMPLEMENT_SAME_ISA
    THEN DO_NOT_ASSUME_IDENTICAL_MICROARCHITECTURE_OR_PERFORMANCE

    IF CLOCK_RATE_IS_HIGHER
    THEN DO_NOT_AUTOMATICALLY_INFER_HIGHER_WORKLOAD_PERFORMANCE

    IF SEMANTIC_IDENTIFIERS_DIFFER
    AND CPU_REFERENT_IS_SAME
    THEN APPLY SEMANTIC_EQUIVALENCE
  }

  CONFIDENCE {
    CONFIDENCE_SCORE =
      WEIGHT(
        SPECIFICATION_COMPLETENESS,
        ISA_CERTAINTY,
        MICROARCHITECTURE_CERTAINTY,
        CONFIGURATION_CERTAINTY,
        EXECUTION_TRACE_COMPLETENESS,
        PERFORMANCE_COUNTER_QUALITY,
        MEASUREMENT_REPRODUCIBILITY,
        PROVENANCE_COMPLETENESS
      )

    LEVELS {
      HIGH
      MODERATE
      LOW
      INSUFFICIENT
    }

    IF MICROARCHITECTURE_IS_UNKNOWN
    THEN REDUCE_MICROARCHITECTURAL_INFERENCE_CONFIDENCE

    IF WORKLOAD_OR_CONFIGURATION_IS_UNKNOWN
    THEN REDUCE_PERFORMANCE_INFERENCE_CONFIDENCE

    IF REPRODUCIBLE_EXECUTION_CONFIRMS_BEHAVIOUR
    THEN INCREASE CONFIDENCE_SCORE
  }

  SEMANTIC_EQUIVALENCE {
    EQUIVALENCE_KEY =
      NORMALISE(
        ENTITY_TYPE,
        CANONICAL_IDENTIFIER,
        ISA,
        MICROARCHITECTURE,
        VERSION,
        CONFIGURATION
      )

    IF EQUIVALENCE_KEY(A) == EQUIVALENCE_KEY(B)
    THEN A SEMANTICALLY_EQUIVALENT_TO B

    ELSE PRESERVE_DISTINCT_ENTITIES
  }

  REASONING_CONSTRAINTS {
    CPU != CORE
    ISA != MICROARCHITECTURE
    INSTRUCTION != EXECUTION
    SPECULATIVE_STATE != COMMITTED_STATE
    CACHE_HIT != MAIN_MEMORY_ACCESS
    CLOCK_RATE != OVERALL_PERFORMANCE
    CORE_COUNT != SINGLE_THREAD_PERFORMANCE
    IPC_IS_WORKLOAD_DEPENDENT
    CACHE_BEHAVIOUR_IS_WORKLOAD_DEPENDENT
    BRANCH_PREDICTION_ACCURACY_IS_WORKLOAD_DEPENDENT
    POWER_AND_TEMPERATURE_AFFECT_SUSTAINED_BEHAVIOUR
    CONFIGURATION_AFFECTS_PERFORMANCE
    PROVENANCE_MUST_BE_PRESERVED
    UNCERTAINTY_MUST_NOT_BE_DISCARDED
  }

  VALIDATION {
    CHECK_ENTITY_TYPES
    CHECK_RELATION_DOMAINS_AND_RANGES
    CHECK_CPU_IDENTIFIERS
    CHECK_ISA
    CHECK_MICROARCHITECTURE
    CHECK_REGISTER_MODEL
    CHECK_PIPELINE_MODEL
    CHECK_CACHE_HIERARCHY
    CHECK_CLOCK_CONTEXT
    CHECK_INTERRUPT_AND_EXCEPTION_CONTEXT
    CHECK_EXECUTION_TRACE
    CHECK_PERFORMANCE_CONTEXT
    CHECK_POWER_AND_THERMAL_CONTEXT
    CHECK_PROVENANCE
    CHECK_CONFIDENCE
    CHECK_SEMANTIC_CONSISTENCY
  }

  OUTPUTS {
    NORMALISED_CPU_ENTITIES
    CPU_COMPONENT_RELATIONS
    ISA_RELATIONS
    MICROARCHITECTURE_RELATIONS
    REGISTER_RELATIONS
    PIPELINE_RELATIONS
    CACHE_RELATIONS
    EXECUTION_TRACES
    BRANCH_RELATIONS
    INTERRUPT_AND_EXCEPTION_RELATIONS
    PERFORMANCE_PROFILES
    POWER_AND_THERMAL_PROFILES
    BOTTLENECK_HYPOTHESES
    CONFIDENCE_SCORES
    EVIDENCE_LINKS
    PROVENANCE_RECORDS
    EXPLANATION_PATHS
  }

  UPDATE_MODEL {
    ON CPU_OR_CONFIGURATION_CHANGE {
      NORMALISE
      ENTITY_RESOLUTION
      UPDATE_CPU_COMPONENTS
      UPDATE_MICROARCHITECTURE
      UPDATE_PIPELINE_MODEL
      UPDATE_CACHE_CONFIGURATION
      RECOMPUTE_AFFECTED_RELATIONS
      UPDATE_CONFIDENCE
      PRESERVE_VERSION_HISTORY
    }

    ON NEW_EXECUTION_OR_PERFORMANCE_DATA {
      LINK_EVIDENCE
      UPDATE_EXECUTION_PROFILE
      UPDATE_BRANCH_PROFILE
      UPDATE_CACHE_PROFILE
      UPDATE_POWER_AND_THERMAL_PROFILE
      REASSESS_BOTTLENECKS
      UPDATE_CONFIDENCE
      RECORD_PROVENANCE
    }

    ON ONTOLOGY_REVISION {
      REMAP_TERMS
      CHECK_SEMANTIC_EQUIVALENCE
      IDENTIFY_DEPRECATED_TERMS
      MIGRATE_RELATIONSHIPS
      PRESERVE_PRIOR_VERSION_REFERENCES
    }
  }

  FLOW_HASH {
    HASH_INPUT =
      CANONICALISE(
        ENTITY_TYPES,
        RELATIONSHIPS,
        RULES,
        CONFIDENCE,
        SEMANTIC_EQUIVALENCE,
        REASONING_CONSTRAINTS,
        UPDATE_MODEL
      )

    FLOW_HASH = SHA256(HASH_INPUT)
  }

  AI_CONSUMPTION {
    INDEX {
      ONTOLOGY
      ENTITY_TYPES
      RELATIONSHIPS
      RULES
      OUTPUTS
    }

    RETRIEVE {
      BY_CPU
      BY_CORE
      BY_EXECUTION_UNIT
      BY_REGISTER
      BY_INSTRUCTION
      BY_ISA
      BY_MICROARCHITECTURE
      BY_PIPELINE
      BY_CACHE
      BY_BRANCH
      BY_INTERRUPT
      BY_EXCEPTION
      BY_PERFORMANCE
      BY_CONFIDENCE
    }

    REASON {
      APPLY_RELATIONSHIPS
      APPLY_RULES
      TRACE_INSTRUCTION_EXECUTION
      TRACE_PIPELINE_STATE
      TRACE_REGISTER_STATE
      TRACE_CACHE_ACCESS
      ANALYSE_BRANCH_PREDICTION
      ANALYSE_INTERRUPTS_AND_EXCEPTIONS
      ANALYSE_PERFORMANCE
      ANALYSE_POWER_AND_THERMAL_BEHAVIOUR
      CHECK_SEMANTIC_EQUIVALENCE
      PRESERVE_UNCERTAINTY
      TRACE_EVIDENCE
      TRACE_PROVENANCE
      GENERATE_EXPLANATION_PATH
    }

    RESPONSE_POLICY {
      DISTINGUISH_CPU_FROM_CORE
      DISTINGUISH_ISA_FROM_MICROARCHITECTURE
      DISTINGUISH_SPECULATIVE_FROM_COMMITTED_STATE
      PRESERVE_WORKLOAD_AND_CONFIGURATION_CONTEXT
      PRESERVE_POWER_AND_THERMAL_CONTEXT
      RETURN_CONFIDENCE_WHEN_AVAILABLE
      RETURN_PROVENANCE_WHEN_AVAILABLE
      AVOID_UNSUPPORTED_CPU_INFERENCE
    }
  }

  TERMINAL {
    RESULT =
      VALIDATED(
        SEMANTICALLY_NORMALISED(
          EVIDENCE_LINKED(
            CONFIDENCE_AWARE(
              CENTRAL_PROCESSING_UNIT_KNOWLEDGE
            )
          )
        )
      )
  }
}

END FLOW