Computer Architecture Ontology

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FLOW ALGEBRA — COMPUTER ARCHITECTURE
Semantic Library
Version: 4.0
Canonical Page:
https://kirethresearch.org/booksai-core/ontologies/computing-ontologies/computer-architecture.html

FLOW COMPUTER_ARCHITECTURE {

  META {
    DOMAIN = "Computing Ontologies"
    SUBDOMAIN = "Computer Architecture"
    ONTOLOGY = "Computer Architecture"
    PURPOSE = "Formalise the principal concepts, components, organisations and execution relationships that define computer architecture."
    LOCALE = "en-GB"
  }

  ENTITY_TYPES {
    COMPUTER_ARCHITECTURE
    COMPUTER_SYSTEM
    PROCESSOR
    CPU
    CORE
    CONTROL_UNIT
    ARITHMETIC_LOGIC_UNIT
    EXECUTION_UNIT
    REGISTER
    REGISTER_FILE
    CACHE
    MEMORY
    MAIN_MEMORY
    VIRTUAL_MEMORY
    STORAGE
    MEMORY_HIERARCHY
    BUS
    INTERCONNECT
    DATA_PATH
    CONTROL_PATH
    MOTHERBOARD
    SYSTEM_ON_CHIP
    DEVICE
    PERIPHERAL
    INPUT_DEVICE
    OUTPUT_DEVICE
    NETWORK_INTERFACE
    IO_CONTROLLER
    MEMORY_CONTROLLER
    INSTRUCTION
    OPCODE
    OPERAND
    INSTRUCTION_SET
    ISA
    MICROARCHITECTURE
    PIPELINE
    PIPELINE_STAGE
    CLOCK
    CLOCK_CYCLE
    INTERRUPT
    ADDRESS
    MEMORY_LOCATION
    DATA
    PROGRAM
    PROCESS
    THREAD
    INPUT
    OUTPUT
    STATE
    EVENT
    RESOURCE
    CONFIGURATION
    VERSION
    LATENCY
    THROUGHPUT
    BANDWIDTH
    POWER
    PERFORMANCE_METRIC
    ERROR
    EVIDENCE
    CONFIDENCE_SCORE
    PROVENANCE_RECORD
  }

  ARCHITECTURAL_DOMAINS {
    INSTRUCTION_SET_ARCHITECTURE
    MICROARCHITECTURE
    PROCESSOR_ARCHITECTURE
    MEMORY_ARCHITECTURE
    CACHE_ARCHITECTURE
    IO_ARCHITECTURE
    INTERCONNECT_ARCHITECTURE
    PIPELINE_ARCHITECTURE
    MULTICORE_ARCHITECTURE
    PARALLEL_ARCHITECTURE
    STORAGE_ARCHITECTURE
    SYSTEM_ON_CHIP_ARCHITECTURE
  }

  RELATIONSHIPS {
    IS_A
    INSTANCE_OF
    PART_OF
    CONTAINS
    HAS_COMPONENT
    CONNECTED_TO
    INTERFACES_WITH
    IMPLEMENTS
    EXECUTES
    FETCHES
    DECODES
    READS
    WRITES
    LOADS
    STORES
    ADDRESSES
    ROUTES_TO
    SENDS
    RECEIVES
    TRANSFERS
    CONTROLS
    CLOCKS
    INTERRUPTS
    HAS_INSTRUCTION_SET
    HAS_MICROARCHITECTURE
    HAS_REGISTER
    HAS_CACHE
    HAS_MEMORY
    HAS_PIPELINE
    HAS_ADDRESS
    HAS_BANDWIDTH
    HAS_LATENCY
    HAS_THROUGHPUT
    HAS_POWER_REQUIREMENT
    HAS_CONFIGURATION
    HAS_VERSION
    DEPENDS_ON
    PRECEDES
    FOLLOWS
    DERIVED_FROM
    INFERRED_FROM
    HAS_EVIDENCE
    HAS_CONFIDENCE
    HAS_PROVENANCE
    MAPS_TO
    SEMANTICALLY_EQUIVALENT_TO
  }

  INPUTS {
    ARCHITECTURE_SPECIFICATIONS
    ISA_DEFINITIONS
    PROCESSOR_SPECIFICATIONS
    MICROARCHITECTURE_DEFINITIONS
    REGISTER_DEFINITIONS
    PIPELINE_DEFINITIONS
    MEMORY_HIERARCHIES
    CACHE_CONFIGURATIONS
    ADDRESS_MAPS
    INTERCONNECT_TOPOLOGIES
    IO_DEFINITIONS
    CLOCK_PARAMETERS
    EXECUTION_TRACES
    PERFORMANCE_METRICS
    POWER_METRICS
    CONFIGURATION_DATA
    VERSION_DATA
    ONTOLOGY_TERMS
  }

  NORMALISE {
    STANDARDISE_IDENTIFIERS
    NORMALISE_ARCHITECTURE_NAMES
    NORMALISE_ISA_NAMES
    NORMALISE_PROCESSOR_NAMES
    NORMALISE_MEMORY_UNITS
    NORMALISE_ADDRESS_FORMATS
    NORMALISE_CLOCK_UNITS
    NORMALISE_BANDWIDTH_UNITS
    NORMALISE_PERFORMANCE_METRICS
    NORMALISE_VERSION_IDENTIFIERS
    RESOLVE_COMPONENT_IDENTITIES
    ALIGN_ONTOLOGY_TERMS
    REMOVE_DUPLICATES
    VALIDATE_METADATA
    PRESERVE_PROVENANCE
  }

  PROCESS ARCHITECTURE_PIPELINE {
    INPUT
      -> ARCHITECTURE_IDENTIFICATION
      -> COMPONENT_RESOLUTION
      -> ISA_MAPPING
      -> MICROARCHITECTURE_MAPPING
      -> MEMORY_MAPPING
      -> INTERCONNECT_MAPPING
      -> EXECUTION_PATH_MAPPING
      -> PERFORMANCE_CONTEXT
      -> VALIDATION
      -> OUTPUT
  }

  PROCESS INSTRUCTION_CYCLE {
    PROGRAM_COUNTER
      -> FETCH

    FETCH
      -> DECODE

    DECODE
      -> OPERAND_FETCH

    OPERAND_FETCH
      -> EXECUTE

    EXECUTE
      -> MEMORY_ACCESS_IF_REQUIRED

    MEMORY_ACCESS_IF_REQUIRED
      -> WRITEBACK

    WRITEBACK
      -> ARCHITECTURAL_STATE_UPDATE
  }

  PROCESS PIPELINE_REASONING {
    INSTRUCTION_STREAM
      -> PIPELINE_STAGE_ASSIGNMENT

    PIPELINE_STAGE_ASSIGNMENT
      -> CONCURRENT_PIPELINE_STATE

    CONCURRENT_PIPELINE_STATE
      -> HAZARD_DETECTION

    HAZARD_DETECTION
      -> STALL_OR_FORWARD_OR_FLUSH_OR_CONTINUE

    RESULT
      -> PIPELINE_STATE_UPDATE
  }

  PROCESS MEMORY_HIERARCHY_REASONING {
    MEMORY_REQUEST
      -> REGISTER_OR_CACHE_LOOKUP

    REGISTER_OR_CACHE_LOOKUP
      -> HIT_OR_MISS

    HIT_OR_MISS
      -> LOWER_MEMORY_LEVEL_IF_REQUIRED

    LOWER_MEMORY_LEVEL_IF_REQUIRED
      -> DATA_RETURN

    DATA_RETURN
      -> CACHE_OR_REGISTER_UPDATE
      -> PROCESSOR
  }

  PROCESS ADDRESS_TRANSLATION {
    VIRTUAL_OR_LOGICAL_ADDRESS
      -> TRANSLATION_MECHANISM

    TRANSLATION_MECHANISM
      -> PHYSICAL_ADDRESS

    PHYSICAL_ADDRESS
      -> MEMORY_OR_DEVICE_MAPPING

    MEMORY_OR_DEVICE_MAPPING
      -> ACCESS_OPERATION
  }

  PROCESS INTERCONNECT_REASONING {
    SOURCE_COMPONENT + DESTINATION_COMPONENT + DATA
      -> TRANSFER_REQUEST

    TRANSFER_REQUEST
      -> ROUTE_SELECTION

    ROUTE_SELECTION
      -> ARBITRATION_IF_REQUIRED

    ARBITRATION_IF_REQUIRED
      -> DATA_TRANSFER

    DATA_TRANSFER
      -> DESTINATION_RECEIPT
  }

  PROCESS MULTICORE_REASONING {
    WORKLOAD
      -> THREAD_OR_TASK_DECOMPOSITION

    THREAD_OR_TASK_DECOMPOSITION
      -> CORE_ASSIGNMENT

    CORE_ASSIGNMENT
      -> PARALLEL_EXECUTION

    PARALLEL_EXECUTION
      -> SHARED_RESOURCE_INTERACTIONS
      -> SYNCHRONISATION

    SYNCHRONISATION
      -> RESULT_COMPOSITION
  }

  PROCESS PERFORMANCE_REASONING {
    ARCHITECTURE + WORKLOAD + CONFIGURATION
      -> EXECUTION_PROFILE

    EXECUTION_PROFILE
      -> LATENCY_ANALYSIS
      -> THROUGHPUT_ANALYSIS
      -> BANDWIDTH_ANALYSIS
      -> CACHE_ANALYSIS
      -> RESOURCE_UTILISATION
      -> POWER_ANALYSIS

    EXECUTION_PROFILE
      -> BOTTLENECK_HYPOTHESIS
  }

  RULES {
    IF PROCESSOR_EXISTS
    THEN REQUIRE {
      INSTRUCTION_SET
      REGISTER_MODEL
      EXECUTION_MODEL
      MEMORY_INTERFACE
    }

    IF INSTRUCTION_EXECUTES
    THEN LINK {
      INSTRUCTION
      OPERANDS
      EXECUTION_UNIT
      STATE_BEFORE
      STATE_AFTER
    }

    IF MEMORY_ACCESS_OCCURS
    THEN REQUIRE {
      ADDRESS
      ACCESS_TYPE
      MEMORY_LEVEL_OR_DEVICE
      EXECUTION_CONTEXT
    }

    IF TWO_PROCESSORS_IMPLEMENT_SAME_ISA
    THEN DO_NOT_ASSUME_IDENTICAL_MICROARCHITECTURE

    IF TWO_PROCESSORS_SHARE_MICROARCHITECTURE_FAMILY
    THEN DO_NOT_ASSUME_IDENTICAL_CONFIGURATION_OR_PERFORMANCE

    IF PERFORMANCE_IS_COMPARED
    THEN REQUIRE {
      WORKLOAD
      CLOCK_CONTEXT
      MEMORY_CONTEXT
      CONFIGURATION
      SOFTWARE_CONTEXT
    }

    IF SEMANTIC_IDENTIFIERS_DIFFER
    AND ARCHITECTURAL_REFERENT_IS_SAME
    THEN APPLY SEMANTIC_EQUIVALENCE
  }

  CONFIDENCE {
    CONFIDENCE_SCORE =
      WEIGHT(
        SPECIFICATION_COMPLETENESS,
        ISA_CERTAINTY,
        MICROARCHITECTURE_CERTAINTY,
        COMPONENT_RESOLUTION,
        CONFIGURATION_CERTAINTY,
        TRACE_COMPLETENESS,
        MEASUREMENT_REPRODUCIBILITY,
        PROVENANCE_COMPLETENESS
      )

    LEVELS {
      HIGH
      MODERATE
      LOW
      INSUFFICIENT
    }

    IF MICROARCHITECTURE_IS_UNKNOWN
    THEN REDUCE_PERFORMANCE_INFERENCE_CONFIDENCE

    IF CONFIGURATION_IS_UNKNOWN
    THEN REDUCE CONFIDENCE_SCORE

    IF REPRODUCIBLE_EXECUTION_CONFIRMS_BEHAVIOUR
    THEN INCREASE CONFIDENCE_SCORE
  }

  SEMANTIC_EQUIVALENCE {
    EQUIVALENCE_KEY =
      NORMALISE(
        ENTITY_TYPE,
        CANONICAL_IDENTIFIER,
        ISA,
        MICROARCHITECTURE,
        VERSION,
        CONFIGURATION
      )

    IF EQUIVALENCE_KEY(A) == EQUIVALENCE_KEY(B)
    THEN A SEMANTICALLY_EQUIVALENT_TO B

    ELSE PRESERVE_DISTINCT_ENTITIES
  }

  REASONING_CONSTRAINTS {
    ISA != MICROARCHITECTURE
    ARCHITECTURE != PHYSICAL_IMPLEMENTATION_INSTANCE
    INSTRUCTION != EXECUTION
    VIRTUAL_ADDRESS != PHYSICAL_ADDRESS
    ADDRESS != DATA
    CACHE != MAIN_MEMORY
    CLOCK_RATE != OVERALL_PERFORMANCE
    CORE_COUNT != APPLICATION_SPEED
    THEORETICAL_BANDWIDTH != OBSERVED_BANDWIDTH
    PERFORMANCE_IS_WORKLOAD_DEPENDENT
    CONFIGURATION_AFFECTS_PERFORMANCE
    SOFTWARE_AFFECTS_OBSERVED_PERFORMANCE
    MEMORY_HIERARCHY_AFFECTS_EXECUTION
    PROVENANCE_MUST_BE_PRESERVED
    UNCERTAINTY_MUST_NOT_BE_DISCARDED
  }

  VALIDATION {
    CHECK_ENTITY_TYPES
    CHECK_ARCHITECTURAL_DOMAINS
    CHECK_RELATION_DOMAINS_AND_RANGES
    CHECK_ARCHITECTURE_IDENTIFIERS
    CHECK_ISA
    CHECK_MICROARCHITECTURE
    CHECK_REGISTER_MODEL
    CHECK_PIPELINE_MODEL
    CHECK_MEMORY_HIERARCHY
    CHECK_ADDRESS_MAPPING
    CHECK_INTERCONNECTS
    CHECK_MULTICORE_RELATIONS
    CHECK_CONFIGURATION
    CHECK_VERSION_CONTEXT
    CHECK_PERFORMANCE_CONTEXT
    CHECK_PROVENANCE
    CHECK_CONFIDENCE
    CHECK_SEMANTIC_CONSISTENCY
  }

  OUTPUTS {
    NORMALISED_ARCHITECTURE_ENTITIES
    ARCHITECTURAL_DOMAIN_RELATIONS
    COMPONENT_GRAPHS
    ISA_RELATIONS
    MICROARCHITECTURE_RELATIONS
    PIPELINE_RELATIONS
    MEMORY_HIERARCHY_RELATIONS
    ADDRESS_MAPPINGS
    INTERCONNECT_RELATIONS
    MULTICORE_RELATIONS
    EXECUTION_PATHS
    PERFORMANCE_PROFILES
    BOTTLENECK_HYPOTHESES
    CONFIDENCE_SCORES
    EVIDENCE_LINKS
    PROVENANCE_RECORDS
    EXPLANATION_PATHS
  }

  UPDATE_MODEL {
    ON ARCHITECTURE_OR_CONFIGURATION_CHANGE {
      NORMALISE
      ENTITY_RESOLUTION
      UPDATE_COMPONENT_GRAPH
      UPDATE_ISA_MAPPING
      UPDATE_MICROARCHITECTURE
      UPDATE_MEMORY_HIERARCHY
      UPDATE_INTERCONNECTS
      RECOMPUTE_AFFECTED_RELATIONS
      UPDATE_CONFIDENCE
      PRESERVE_VERSION_HISTORY
    }

    ON NEW_EXECUTION_OR_PERFORMANCE_DATA {
      LINK_EVIDENCE
      UPDATE_EXECUTION_PROFILE
      REASSESS_PERFORMANCE_RELATIONS
      REASSESS_BOTTLENECKS
      UPDATE_CONFIDENCE
      RECORD_PROVENANCE
    }

    ON ONTOLOGY_REVISION {
      REMAP_TERMS
      CHECK_SEMANTIC_EQUIVALENCE
      IDENTIFY_DEPRECATED_TERMS
      MIGRATE_RELATIONSHIPS
      PRESERVE_PRIOR_VERSION_REFERENCES
    }
  }

  FLOW_HASH {
    HASH_INPUT =
      CANONICALISE(
        ENTITY_TYPES,
        ARCHITECTURAL_DOMAINS,
        RELATIONSHIPS,
        RULES,
        CONFIDENCE,
        SEMANTIC_EQUIVALENCE,
        REASONING_CONSTRAINTS,
        UPDATE_MODEL
      )

    FLOW_HASH = SHA256(HASH_INPUT)
  }

  AI_CONSUMPTION {
    INDEX {
      ONTOLOGY
      ENTITY_TYPES
      ARCHITECTURAL_DOMAINS
      RELATIONSHIPS
      RULES
      OUTPUTS
    }

    RETRIEVE {
      BY_ARCHITECTURE
      BY_PROCESSOR
      BY_CORE
      BY_ISA
      BY_MICROARCHITECTURE
      BY_REGISTER
      BY_PIPELINE
      BY_CACHE
      BY_MEMORY
      BY_ADDRESS
      BY_INTERCONNECT
      BY_PERFORMANCE
      BY_CONFIDENCE
    }

    REASON {
      APPLY_RELATIONSHIPS
      APPLY_RULES
      TRACE_INSTRUCTION_EXECUTION
      TRACE_PIPELINE_STATE
      TRACE_MEMORY_ACCESS
      TRACE_ADDRESS_TRANSLATION
      TRACE_INTERCONNECT_PATH
      ANALYSE_MULTICORE_EXECUTION
      ANALYSE_RESOURCE_USAGE
      ANALYSE_PERFORMANCE
      CHECK_SEMANTIC_EQUIVALENCE
      PRESERVE_UNCERTAINTY
      TRACE_EVIDENCE
      TRACE_PROVENANCE
      GENERATE_EXPLANATION_PATH
    }

    RESPONSE_POLICY {
      DISTINGUISH_ISA_FROM_MICROARCHITECTURE
      DISTINGUISH_ARCHITECTURE_FROM_IMPLEMENTATION
      PRESERVE_MEMORY_AND_ADDRESS_CONTEXT
      PRESERVE_WORKLOAD_AND_CONFIGURATION_CONTEXT
      RETURN_CONFIDENCE_WHEN_AVAILABLE
      RETURN_PROVENANCE_WHEN_AVAILABLE
      AVOID_UNSUPPORTED_ARCHITECTURAL_INFERENCE
    }
  }

  TERMINAL {
    RESULT =
      VALIDATED(
        SEMANTICALLY_NORMALISED(
          EVIDENCE_LINKED(
            CONFIDENCE_AWARE(
              COMPUTER_ARCHITECTURE_KNOWLEDGE
            )
          )
        )
      )
  }
}

END FLOW