RAM Ontology

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FLOW ALGEBRA — RAM ONTOLOGY
Semantic Library
Version: 4.0
Canonical Page:
https://kirethresearch.org/booksai-core/ontologies/computing-ontologies/computer-hardware/ram-ontology.html

FLOW RAM_ONTOLOGY {

  META {
    DOMAIN = "Computing Ontologies"
    SUBDOMAIN = "Computer Hardware"
    ONTOLOGY = "RAM Ontology"
    PURPOSE = "Formalise random-access memory technologies, modules, cells, banks, channels, addressing, read/write operations, timings, refresh, performance and reliability relationships."
    LOCALE = "en-GB"
  }

  ENTITY_TYPES {
    RAM
    RANDOM_ACCESS_MEMORY
    VOLATILE_MEMORY
    DRAM
    SRAM
    SDRAM
    DDR_SDRAM
    DDR2
    DDR3
    DDR4
    DDR5
    LPDDR
    MEMORY_MODULE
    DIMM
    SODIMM
    MEMORY_CHIP
    MEMORY_CELL
    MEMORY_BANK
    BANK_GROUP
    MEMORY_RANK
    MEMORY_CHANNEL
    MEMORY_CONTROLLER
    MEMORY_BUS
    DATA_BUS
    ADDRESS_BUS
    COMMAND_BUS
    ADDRESS
    ROW_ADDRESS
    COLUMN_ADDRESS
    BANK_ADDRESS
    MEMORY_LOCATION
    DATA
    BIT
    BYTE
    WORD
    READ_OPERATION
    WRITE_OPERATION
    ACTIVATE_COMMAND
    PRECHARGE_COMMAND
    REFRESH_COMMAND
    MEMORY_REQUEST
    MEMORY_RESPONSE
    ROW_BUFFER
    CLOCK
    CLOCK_RATE
    DATA_RATE
    TIMING_PARAMETER
    CAS_LATENCY
    RAS_TO_CAS_DELAY
    ROW_PRECHARGE_TIME
    ACTIVE_TO_PRECHARGE_TIME
    REFRESH_INTERVAL
    CAPACITY
    BANDWIDTH
    LATENCY
    VOLTAGE
    POWER
    TEMPERATURE
    ECC
    PARITY
    BIT_ERROR
    CORRECTABLE_ERROR
    UNCORRECTABLE_ERROR
    STATE
    EVENT
    CONFIGURATION
    HARDWARE_REVISION
    VERSION
    PERFORMANCE_METRIC
    EVIDENCE
    CONFIDENCE_SCORE
    PROVENANCE_RECORD
  }

  RELATIONSHIPS {
    IS_A
    INSTANCE_OF
    PART_OF
    CONTAINS
    HAS_MODULE
    HAS_CHIP
    HAS_CELL
    HAS_BANK
    HAS_BANK_GROUP
    HAS_RANK
    HAS_CHANNEL
    HAS_CONTROLLER
    HAS_ROW
    HAS_COLUMN
    HAS_ADDRESS
    STORES
    READS
    WRITES
    ACTIVATES
    PRECHARGES
    REFRESHES
    ADDRESSES
    TRANSFERS
    RECEIVES
    RETURNS
    HAS_CAPACITY
    HAS_CLOCK_RATE
    HAS_DATA_RATE
    HAS_TIMING
    HAS_LATENCY
    HAS_BANDWIDTH
    HAS_VOLTAGE
    HAS_POWER
    HAS_TEMPERATURE
    HAS_ECC
    DETECTS_ERROR
    CORRECTS_ERROR
    HAS_STATE
    TRANSITIONS_TO
    HAS_CONFIGURATION
    HAS_HARDWARE_REVISION
    HAS_VERSION
    DEPENDS_ON
    PRECEDES
    FOLLOWS
    DERIVED_FROM
    INFERRED_FROM
    HAS_EVIDENCE
    HAS_CONFIDENCE
    HAS_PROVENANCE
    MAPS_TO
    SEMANTICALLY_EQUIVALENT_TO
  }

  INPUTS {
    RAM_SPECIFICATIONS
    MEMORY_TYPE_DATA
    MODULE_DATA
    CHIP_DATA
    CAPACITY_DATA
    BANK_AND_RANK_DATA
    CHANNEL_CONFIGURATION
    ADDRESS_MAPPING
    MEMORY_TIMINGS
    CLOCK_PARAMETERS
    DATA_RATE_DATA
    VOLTAGE_DATA
    POWER_DATA
    TEMPERATURE_DATA
    READ_WRITE_TRACES
    REFRESH_DATA
    ECC_DATA
    ERROR_LOGS
    CONFIGURATION_DATA
    HARDWARE_REVISION_DATA
    VERSION_DATA
    ONTOLOGY_TERMS
  }

  NORMALISE {
    STANDARDISE_RAM_IDENTIFIERS
    NORMALISE_MEMORY_TYPE_NAMES
    NORMALISE_MODULE_TYPES
    NORMALISE_CAPACITY_UNITS
    NORMALISE_ADDRESS_FORMATS
    NORMALISE_CLOCK_UNITS
    NORMALISE_DATA_RATE_UNITS
    NORMALISE_TIMING_PARAMETERS
    NORMALISE_VOLTAGE_UNITS
    NORMALISE_POWER_UNITS
    NORMALISE_TEMPERATURE_UNITS
    NORMALISE_ERROR_TYPES
    NORMALISE_HARDWARE_REVISIONS
    NORMALISE_VERSION_IDENTIFIERS
    RESOLVE_MODULE_AND_CHIP_IDENTITIES
    ALIGN_ONTOLOGY_TERMS
    REMOVE_DUPLICATES
    VALIDATE_METADATA
    PRESERVE_PROVENANCE
  }

  PROCESS RAM_ACCESS_PIPELINE {
    MEMORY_REQUEST
      -> ADDRESS_MAPPING
      -> CHANNEL_RANK_BANK_SELECTION
      -> ROW_STATE_CHECK
      -> ACTIVATE_IF_REQUIRED
      -> READ_OR_WRITE
      -> DATA_TRANSFER
      -> PRECHARGE_IF_REQUIRED
      -> MEMORY_RESPONSE
  }

  PROCESS ADDRESS_REASONING {
    MEMORY_ADDRESS
      -> CHANNEL_MAPPING
      -> RANK_MAPPING
      -> BANK_OR_BANK_GROUP_MAPPING
      -> ROW_MAPPING
      -> COLUMN_MAPPING

    MAPPED_ADDRESS
      -> PHYSICAL_RAM_LOCATION
  }

  PROCESS DRAM_READ {
    READ_REQUEST
      -> BANK_SELECTION

    BANK_SELECTION
      -> ROW_BUFFER_CHECK

    ROW_HIT
      -> COLUMN_READ

    ROW_MISS
      -> PRECHARGE_IF_REQUIRED
      -> ACTIVATE_ROW
      -> COLUMN_READ

    COLUMN_READ
      -> DATA_TRANSFER
  }

  PROCESS DRAM_WRITE {
    WRITE_REQUEST + DATA
      -> BANK_SELECTION

    BANK_SELECTION
      -> ROW_BUFFER_CHECK

    REQUIRED_ROW_NOT_ACTIVE
      -> PRECHARGE_IF_REQUIRED
      -> ACTIVATE_ROW

    ACTIVE_ROW
      -> COLUMN_WRITE

    COLUMN_WRITE
      -> UPDATED_MEMORY_STATE
  }

  PROCESS REFRESH_REASONING {
    DRAM
      -> REFRESH_REQUIREMENT

    REFRESH_SCHEDULE
      -> REFRESH_COMMAND

    REFRESH_COMMAND
      -> CELL_CHARGE_RESTORATION

    REFRESH_OPERATION
      -> TEMPORARY_ACCESS_CONSTRAINT
  }

  PROCESS CHANNEL_REASONING {
    MEMORY_CONTROLLER
      -> CHANNEL_SET

    MEMORY_REQUESTS
      -> CHANNEL_SELECTION

    CHANNEL_SELECTION
      -> REQUEST_SCHEDULING

    MULTIPLE_ACTIVE_CHANNELS
      -> PARALLEL_MEMORY_TRANSFERS
  }

  PROCESS ECC_REASONING {
    STORED_OR_TRANSFERRED_DATA
      -> ECC_CHECK

    ECC_CHECK
      -> NO_ERROR
      OR -> CORRECTABLE_ERROR
      OR -> UNCORRECTABLE_ERROR

    CORRECTABLE_ERROR
      -> ERROR_CORRECTION
      -> CORRECTED_DATA

    UNCORRECTABLE_ERROR
      -> ERROR_REPORT
  }

  PROCESS PERFORMANCE_REASONING {
    RAM + WORKLOAD + CONFIGURATION
      -> RAM_PROFILE

    RAM_PROFILE
      -> EFFECTIVE_LATENCY
      -> EFFECTIVE_BANDWIDTH
      -> ROW_HIT_RATE
      -> BANK_CONFLICT_RATE
      -> CHANNEL_UTILISATION
      -> QUEUEING_DELAY
      -> REFRESH_OVERHEAD

    RAM_PROFILE
      -> BOTTLENECK_HYPOTHESIS
  }

  RULES {
    IF RAM_ACCESS_OCCURS
    THEN REQUIRE {
      ADDRESS
      ACCESS_TYPE
      MEMORY_CONFIGURATION
      TIMING_CONTEXT
    }

    IF DRAM_IS_USED
    THEN REQUIRE REFRESH_CONTEXT

    IF ROW_IS_NOT_ACTIVE
    THEN DO_NOT_ASSERT_DIRECT_COLUMN_ACCESS_WITHOUT_ACTIVATION

    IF MEMORY_MODULES_HAVE_SAME_CAPACITY
    THEN DO_NOT_ASSUME_SAME_TYPE_TIMINGS_OR_PERFORMANCE

    IF DATA_RATE_IS_HIGHER
    THEN DO_NOT_AUTOMATICALLY_INFER_LOWER_ACCESS_LATENCY

    IF MULTI_CHANNEL_CONFIGURATION_IS_CLAIMED
    THEN REQUIRE CHANNEL_POPULATION_AND_CONTROLLER_CONTEXT

    IF ECC_CORRECTS_ERROR
    THEN PRESERVE ORIGINAL_ERROR_AND_CORRECTION_EVENT

    IF SEMANTIC_IDENTIFIERS_DIFFER
    AND RAM_REFERENT_IS_SAME
    THEN APPLY SEMANTIC_EQUIVALENCE
  }

  CONFIDENCE {
    CONFIDENCE_SCORE =
      WEIGHT(
        RAM_SPECIFICATION_COMPLETENESS,
        MEMORY_TYPE_CERTAINTY,
        ADDRESS_MAPPING_CERTAINTY,
        TIMING_CERTAINTY,
        CHANNEL_CONFIGURATION_CERTAINTY,
        TRACE_COMPLETENESS,
        ERROR_LOG_QUALITY,
        PROVENANCE_COMPLETENESS
      )

    LEVELS {
      HIGH
      MODERATE
      LOW
      INSUFFICIENT
    }

    IF TIMING_OR_CHANNEL_CONFIGURATION_IS_UNKNOWN
    THEN REDUCE_PERFORMANCE_INFERENCE_CONFIDENCE

    IF ADDRESS_MAPPING_IS_UNKNOWN
    THEN REDUCE_BANK_AND_ROW_INFERENCE_CONFIDENCE

    IF REPRODUCIBLE_MEMORY_TRACE_CONFIRMS_BEHAVIOUR
    THEN INCREASE CONFIDENCE_SCORE
  }

  SEMANTIC_EQUIVALENCE {
    EQUIVALENCE_KEY =
      NORMALISE(
        ENTITY_TYPE,
        CANONICAL_IDENTIFIER,
        MEMORY_GENERATION,
        CAPACITY,
        DATA_RATE,
        TIMING_PROFILE,
        HARDWARE_REVISION,
        CONFIGURATION
      )

    IF EQUIVALENCE_KEY(A) == EQUIVALENCE_KEY(B)
    THEN A SEMANTICALLY_EQUIVALENT_TO B

    ELSE PRESERVE_DISTINCT_ENTITIES
  }

  REASONING_CONSTRAINTS {
    RAM != STORAGE
    DRAM != SRAM
    CAPACITY != PERFORMANCE
    DATA_RATE != ACCESS_LATENCY
    CLOCK_RATE != EFFECTIVE_DATA_RATE
    CAS_LATENCY_VALUE_ALONE != ABSOLUTE_LATENCY
    ROW_HIT != CACHE_HIT
    BANK != CHANNEL
    RANK != CHANNEL
    REFRESH_AFFECTS_DRAM_AVAILABILITY
    MULTI_CHANNEL_BANDWIDTH_DEPENDS_ON_POPULATION_AND_WORKLOAD
    TIMINGS_AFFECT_ACCESS_BEHAVIOUR
    VOLTAGE_AND_TEMPERATURE_MAY_AFFECT_RELIABILITY
    ECC_DETECTION != ALWAYS_CORRECTION
    PROVENANCE_MUST_BE_PRESERVED
    UNCERTAINTY_MUST_NOT_BE_DISCARDED
  }

  VALIDATION {
    CHECK_ENTITY_TYPES
    CHECK_RELATION_DOMAINS_AND_RANGES
    CHECK_RAM_IDENTIFIER
    CHECK_MEMORY_TYPE
    CHECK_MODULE_TYPE
    CHECK_CAPACITY
    CHECK_CHANNEL_CONFIGURATION
    CHECK_RANK_AND_BANK_CONFIGURATION
    CHECK_ADDRESS_MAPPING
    CHECK_TIMING_PARAMETERS
    CHECK_DATA_RATE
    CHECK_VOLTAGE
    CHECK_REFRESH_CONTEXT
    CHECK_READ_WRITE_RELATIONS
    CHECK_ECC_RELATIONS
    CHECK_ERROR_RELATIONS
    CHECK_PERFORMANCE_CONTEXT
    CHECK_HARDWARE_REVISION
    CHECK_VERSION_CONTEXT
    CHECK_PROVENANCE
    CHECK_CONFIDENCE
    CHECK_SEMANTIC_CONSISTENCY
  }

  OUTPUTS {
    NORMALISED_RAM_ENTITIES
    MEMORY_TYPE_RELATIONS
    MODULE_AND_CHIP_RELATIONS
    CHANNEL_RELATIONS
    RANK_AND_BANK_RELATIONS
    ADDRESS_MAPPING_RELATIONS
    READ_WRITE_RELATIONS
    ROW_BUFFER_RELATIONS
    REFRESH_RELATIONS
    ECC_AND_ERROR_RELATIONS
    RAM_STATE_TRANSITIONS
    ACCESS_TRACES
    PERFORMANCE_PROFILES
    BOTTLENECK_HYPOTHESES
    CONFIDENCE_SCORES
    EVIDENCE_LINKS
    PROVENANCE_RECORDS
    EXPLANATION_PATHS
  }

  UPDATE_MODEL {
    ON RAM_OR_CONFIGURATION_CHANGE {
      NORMALISE
      ENTITY_RESOLUTION
      UPDATE_MODULE_TOPOLOGY
      UPDATE_CHANNEL_CONFIGURATION
      UPDATE_ADDRESS_MAPPING
      UPDATE_TIMING_MODEL
      UPDATE_REFRESH_MODEL
      UPDATE_ECC_MODEL
      RECOMPUTE_AFFECTED_RELATIONS
      UPDATE_CONFIDENCE
      PRESERVE_VERSION_HISTORY
    }

    ON NEW_ACCESS_ERROR_OR_PERFORMANCE_DATA {
      LINK_EVIDENCE
      UPDATE_ACCESS_TRACE
      UPDATE_ROW_AND_BANK_PROFILE
      UPDATE_ERROR_PROFILE
      UPDATE_PERFORMANCE_PROFILE
      REASSESS_BOTTLENECKS
      UPDATE_CONFIDENCE
      RECORD_PROVENANCE
    }

    ON ONTOLOGY_REVISION {
      REMAP_TERMS
      CHECK_SEMANTIC_EQUIVALENCE
      IDENTIFY_DEPRECATED_TERMS
      MIGRATE_RELATIONSHIPS
      PRESERVE_PRIOR_VERSION_REFERENCES
    }
  }

  FLOW_HASH {
    HASH_INPUT =
      CANONICALISE(
        ENTITY_TYPES,
        RELATIONSHIPS,
        RULES,
        CONFIDENCE,
        SEMANTIC_EQUIVALENCE,
        REASONING_CONSTRAINTS,
        UPDATE_MODEL
      )

    FLOW_HASH = SHA256(HASH_INPUT)
  }

  AI_CONSUMPTION {
    INDEX {
      ONTOLOGY
      ENTITY_TYPES
      RELATIONSHIPS
      RULES
      OUTPUTS
    }

    RETRIEVE {
      BY_RAM
      BY_MEMORY_TYPE
      BY_MODULE
      BY_CHIP
      BY_CHANNEL
      BY_RANK
      BY_BANK
      BY_ADDRESS
      BY_TIMING
      BY_REFRESH
      BY_ECC
      BY_ERROR
      BY_PERFORMANCE
      BY_CONFIDENCE
    }

    REASON {
      APPLY_RELATIONSHIPS
      APPLY_RULES
      TRACE_RAM_ACCESS
      TRACE_ADDRESS_MAPPING
      ANALYSE_DRAM_READS_AND_WRITES
      ANALYSE_ROW_BUFFER_BEHAVIOUR
      ANALYSE_CHANNELS
      ANALYSE_REFRESH
      ANALYSE_ECC_AND_ERRORS
      ANALYSE_PERFORMANCE
      CHECK_SEMANTIC_EQUIVALENCE
      PRESERVE_UNCERTAINTY
      TRACE_EVIDENCE
      TRACE_PROVENANCE
      GENERATE_EXPLANATION_PATH
    }

    RESPONSE_POLICY {
      DISTINGUISH_RAM_FROM_STORAGE
      DISTINGUISH_MEMORY_GENERATION_AND_TECHNOLOGY
      PRESERVE_CHANNEL_RANK_BANK_AND_TIMING_CONTEXT
      DISTINGUISH_DATA_RATE_FROM_LATENCY
      PRESERVE_REFRESH_AND_ECC_CONTEXT
      RETURN_CONFIDENCE_WHEN_AVAILABLE
      RETURN_PROVENANCE_WHEN_AVAILABLE
      AVOID_UNSUPPORTED_RAM_INFERENCE
    }
  }

  TERMINAL {
    RESULT =
      VALIDATED(
        SEMANTICALLY_NORMALISED(
          EVIDENCE_LINKED(
            CONFIDENCE_AWARE(
              RAM_KNOWLEDGE
            )
          )
        )
      )
  }
}

END FLOW