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FLOW ALGEBRA — PROCESSOR ONTOLOGY
Semantic Library
Version: 4.0
Canonical Page:
https://kirethresearch.org/booksai-core/ontologies/computing-ontologies/computer-hardware/processor-ontology-2.html
FLOW PROCESSOR_ONTOLOGY {
META {
DOMAIN = "Computing Ontologies"
SUBDOMAIN = "Computer Hardware"
ONTOLOGY = "Processor Ontology"
PURPOSE = "Formalise processor hardware, cores, execution resources, instruction processing, memory interfaces, operating states, power, thermal behaviour and performance relationships."
LOCALE = "en-GB"
}
ENTITY_TYPES {
PROCESSOR
CPU
MICROPROCESSOR
MULTI_CORE_PROCESSOR
SYSTEM_ON_CHIP
CORE
PHYSICAL_CORE
LOGICAL_PROCESSOR
HARDWARE_THREAD
CONTROL_UNIT
ARITHMETIC_LOGIC_UNIT
EXECUTION_UNIT
INTEGER_UNIT
FLOATING_POINT_UNIT
VECTOR_UNIT
LOAD_STORE_UNIT
BRANCH_UNIT
REGISTER
REGISTER_FILE
CACHE
L1_CACHE
L2_CACHE
L3_CACHE
MEMORY_CONTROLLER
INTERCONNECT
BUS
CLOCK
CLOCK_DOMAIN
CLOCK_RATE
INSTRUCTION
OPCODE
OPERAND
INSTRUCTION_SET
ISA
MICROARCHITECTURE
PIPELINE
PIPELINE_STAGE
BRANCH_PREDICTOR
PREFETCHER
INTERRUPT
EXCEPTION
ADDRESS
DATA
PROCESS
THREAD
WORKLOAD
STATE
POWER_STATE
PERFORMANCE_STATE
IDLE_STATE
ACTIVE_STATE
FREQUENCY
VOLTAGE
CURRENT
POWER
TEMPERATURE
THERMAL_LIMIT
TDP
LATENCY
THROUGHPUT
UTILISATION
PERFORMANCE_METRIC
CONFIGURATION
HARDWARE_REVISION
VERSION
FAILURE
ERROR
EVIDENCE
CONFIDENCE_SCORE
PROVENANCE_RECORD
}
RELATIONSHIPS {
IS_A
INSTANCE_OF
PART_OF
CONTAINS
HAS_CORE
HAS_THREAD
HAS_UNIT
HAS_REGISTER
HAS_CACHE
HAS_MEMORY_CONTROLLER
HAS_INTERCONNECT
IMPLEMENTS
EXECUTES
FETCHES
DECODES
COMPUTES
LOADS
STORES
READS
WRITES
ADDRESSES
PREDICTS
PREFETCHES
CLOCKS
INTERRUPTS
RAISES_EXCEPTION
HAS_INSTRUCTION_SET
HAS_MICROARCHITECTURE
HAS_PIPELINE
HAS_CLOCK_RATE
HAS_FREQUENCY
HAS_VOLTAGE
HAS_POWER
HAS_TEMPERATURE
HAS_THERMAL_LIMIT
HAS_TDP
HAS_LATENCY
HAS_THROUGHPUT
HAS_UTILISATION
HAS_STATE
TRANSITIONS_TO
HAS_CONFIGURATION
HAS_HARDWARE_REVISION
HAS_VERSION
FAILS_WITH
DEPENDS_ON
PRECEDES
FOLLOWS
DERIVED_FROM
INFERRED_FROM
HAS_EVIDENCE
HAS_CONFIDENCE
HAS_PROVENANCE
MAPS_TO
SEMANTICALLY_EQUIVALENT_TO
}
INPUTS {
PROCESSOR_SPECIFICATIONS
MANUFACTURER_DATA
MODEL_DATA
ISA_DEFINITIONS
MICROARCHITECTURE_DEFINITIONS
CORE_TOPOLOGIES
CACHE_CONFIGURATIONS
CLOCK_PARAMETERS
VOLTAGE_DATA
POWER_DATA
TEMPERATURE_DATA
THERMAL_LIMITS
EXECUTION_TRACES
PERFORMANCE_COUNTERS
WORKLOAD_DATA
CONFIGURATION_DATA
HARDWARE_REVISION_DATA
VERSION_DATA
FAILURE_RECORDS
ONTOLOGY_TERMS
}
NORMALISE {
STANDARDISE_PROCESSOR_IDENTIFIERS
NORMALISE_MANUFACTURER_NAMES
NORMALISE_MODEL_NAMES
NORMALISE_ISA_NAMES
NORMALISE_MICROARCHITECTURE_NAMES
NORMALISE_CORE_AND_THREAD_IDENTIFIERS
NORMALISE_CACHE_UNITS
NORMALISE_FREQUENCY_UNITS
NORMALISE_VOLTAGE_UNITS
NORMALISE_POWER_UNITS
NORMALISE_TEMPERATURE_UNITS
NORMALISE_PERFORMANCE_METRICS
NORMALISE_HARDWARE_REVISIONS
NORMALISE_VERSION_IDENTIFIERS
RESOLVE_COMPONENT_IDENTITIES
ALIGN_ONTOLOGY_TERMS
REMOVE_DUPLICATES
VALIDATE_METADATA
PRESERVE_PROVENANCE
}
PROCESS PROCESSOR_REASONING_PIPELINE {
INPUT
-> PROCESSOR_IDENTIFICATION
-> ISA_RESOLUTION
-> MICROARCHITECTURE_RESOLUTION
-> CORE_AND_THREAD_TOPOLOGY
-> CACHE_AND_MEMORY_INTERFACE_MAPPING
-> EXECUTION_RESOURCE_MAPPING
-> POWER_AND_THERMAL_MAPPING
-> PERFORMANCE_CONTEXT
-> VALIDATION
-> OUTPUT
}
PROCESS INSTRUCTION_EXECUTION {
INSTRUCTION_STREAM
-> FETCH
-> DECODE
-> OPERAND_RESOLUTION
-> EXECUTION_RESOURCE_SELECTION
-> EXECUTE
-> MEMORY_ACCESS_IF_REQUIRED
-> WRITEBACK
-> RETIRE_OR_COMMIT
}
PROCESS CORE_REASONING {
PROCESSOR
-> CORE_SET
CORE_SET
-> PHYSICAL_CORE_IDENTIFICATION
PHYSICAL_CORE_IDENTIFICATION
-> HARDWARE_THREAD_OR_LOGICAL_PROCESSOR_MAPPING
THREAD_ASSIGNMENT
-> CORE_EXECUTION_CONTEXT
}
PROCESS CACHE_AND_MEMORY_REASONING {
MEMORY_REQUEST
-> CACHE_HIERARCHY_LOOKUP
CACHE_HIERARCHY_LOOKUP
-> HIT_OR_MISS
MISS
-> MEMORY_CONTROLLER_REQUEST
MEMORY_CONTROLLER_REQUEST
-> MAIN_MEMORY_ACCESS
DATA_RETURN
-> PROCESSOR
}
PROCESS FREQUENCY_AND_VOLTAGE_REASONING {
PERFORMANCE_DEMAND + POWER_POLICY + THERMAL_STATE
-> TARGET_PERFORMANCE_STATE
TARGET_PERFORMANCE_STATE
-> FREQUENCY_SELECTION
-> VOLTAGE_SELECTION
FREQUENCY_SELECTION + VOLTAGE_SELECTION
-> PROCESSOR_OPERATING_POINT
}
PROCESS THERMAL_REASONING {
PROCESSOR_ACTIVITY
-> POWER_CONSUMPTION
POWER_CONSUMPTION
-> HEAT_GENERATION
HEAT_GENERATION + COOLING_CAPABILITY + AMBIENT_CONTEXT
-> PROCESSOR_TEMPERATURE
PROCESSOR_TEMPERATURE
-> THERMAL_LIMIT_CHECK
THERMAL_LIMIT_EXCEEDED_OR_APPROACHED
-> THROTTLING_OR_PROTECTION_ACTION
}
PROCESS PERFORMANCE_REASONING {
PROCESSOR + WORKLOAD + CONFIGURATION
-> EXECUTION_PROFILE
EXECUTION_PROFILE
-> INSTRUCTION_THROUGHPUT
-> LATENCY
-> IPC_OR_RELATED_METRICS
-> CACHE_BEHAVIOUR
-> BRANCH_BEHAVIOUR
-> CORE_UTILISATION
-> MEMORY_STALLS
-> POWER_AND_THERMAL_PROFILE
EXECUTION_PROFILE
-> BOTTLENECK_HYPOTHESIS
}
PROCESS FAILURE_REASONING {
OBSERVED_PROCESSOR_SYMPTOM
-> FAILURE_CANDIDATES
FAILURE_CANDIDATES
-> POWER_CHECK
-> THERMAL_CHECK
-> CLOCK_CHECK
-> MEMORY_INTERFACE_CHECK
-> EXECUTION_ERROR_CHECK
EVIDENCE
-> ROOT_CAUSE_HYPOTHESIS
-> CONFIDENCE_SCORE
}
RULES {
IF ENTITY == PROCESSOR
THEN REQUIRE {
ISA_OR_PROCESSING_MODEL
CORE_OR_EXECUTION_TOPOLOGY
MEMORY_INTERFACE
OPERATING_CONTEXT
}
IF TWO_PROCESSORS_IMPLEMENT_SAME_ISA
THEN DO_NOT_ASSUME_IDENTICAL_MICROARCHITECTURE_OR_PERFORMANCE
IF CLOCK_RATE_IS_HIGHER
THEN DO_NOT_AUTOMATICALLY_INFER_HIGHER_WORKLOAD_PERFORMANCE
IF CORE_COUNT_IS_HIGHER
THEN DO_NOT_AUTOMATICALLY_INFER_PROPORTIONAL_SPEEDUP
IF PROCESSOR_TEMPERATURE_REACHES_THERMAL_LIMIT
THEN CHECK_THROTTLING_OR_PROTECTION_STATE
IF PERFORMANCE_IS_COMPARED
THEN REQUIRE WORKLOAD_CONFIGURATION_MEMORY_POWER_AND_THERMAL_CONTEXT
IF FAILURE_IS_OBSERVED
THEN DO_NOT_ASSERT_PROCESSOR_ROOT_CAUSE_WITHOUT_EVIDENCE_CHAIN
IF SEMANTIC_IDENTIFIERS_DIFFER
AND PROCESSOR_REFERENT_IS_SAME
THEN APPLY SEMANTIC_EQUIVALENCE
}
CONFIDENCE {
CONFIDENCE_SCORE =
WEIGHT(
SPECIFICATION_COMPLETENESS,
MODEL_IDENTIFICATION_CERTAINTY,
ISA_CERTAINTY,
MICROARCHITECTURE_CERTAINTY,
CONFIGURATION_CERTAINTY,
PERFORMANCE_DATA_QUALITY,
POWER_AND_THERMAL_DATA_QUALITY,
PROVENANCE_COMPLETENESS
)
LEVELS {
HIGH
MODERATE
LOW
INSUFFICIENT
}
IF MICROARCHITECTURE_OR_CONFIGURATION_IS_UNKNOWN
THEN REDUCE_PERFORMANCE_INFERENCE_CONFIDENCE
IF POWER_OR_THERMAL_CONTEXT_IS_UNKNOWN
THEN REDUCE_SUSTAINED_PERFORMANCE_CONFIDENCE
IF REPRODUCIBLE_BENCHMARK_OR_TRACE_CONFIRMS_BEHAVIOUR
THEN INCREASE CONFIDENCE_SCORE
}
SEMANTIC_EQUIVALENCE {
EQUIVALENCE_KEY =
NORMALISE(
ENTITY_TYPE,
MANUFACTURER,
MODEL,
HARDWARE_REVISION,
ISA,
MICROARCHITECTURE,
CONFIGURATION
)
IF EQUIVALENCE_KEY(A) == EQUIVALENCE_KEY(B)
THEN A SEMANTICALLY_EQUIVALENT_TO B
ELSE PRESERVE_DISTINCT_ENTITIES
}
REASONING_CONSTRAINTS {
PROCESSOR != CORE
PHYSICAL_CORE != LOGICAL_PROCESSOR
ISA != MICROARCHITECTURE
CLOCK_RATE != OVERALL_PERFORMANCE
CORE_COUNT != APPLICATION_SPEED
TDP != ACTUAL_POWER_CONSUMPTION
TEMPERATURE != POWER
PEAK_FREQUENCY != SUSTAINED_FREQUENCY
THEORETICAL_THROUGHPUT != OBSERVED_THROUGHPUT
PERFORMANCE_IS_WORKLOAD_DEPENDENT
PERFORMANCE_IS_MEMORY_DEPENDENT
POWER_AND_THERMAL_LIMITS_AFFECT_SUSTAINED_BEHAVIOUR
CONFIGURATION_AND_FIRMWARE_MAY_AFFECT_PROCESSOR_BEHAVIOUR
FAILURE_SYMPTOM != ROOT_CAUSE
PROVENANCE_MUST_BE_PRESERVED
UNCERTAINTY_MUST_NOT_BE_DISCARDED
}
VALIDATION {
CHECK_ENTITY_TYPES
CHECK_RELATION_DOMAINS_AND_RANGES
CHECK_PROCESSOR_IDENTIFIER
CHECK_ISA
CHECK_MICROARCHITECTURE
CHECK_CORE_TOPOLOGY
CHECK_THREAD_TOPOLOGY
CHECK_CACHE_HIERARCHY
CHECK_MEMORY_INTERFACE
CHECK_FREQUENCY_AND_VOLTAGE_CONTEXT
CHECK_POWER_CONTEXT
CHECK_THERMAL_CONTEXT
CHECK_EXECUTION_TRACE
CHECK_PERFORMANCE_CONTEXT
CHECK_CONFIGURATION
CHECK_HARDWARE_REVISION
CHECK_VERSION_CONTEXT
CHECK_FAILURE_RELATIONS
CHECK_PROVENANCE
CHECK_CONFIDENCE
CHECK_SEMANTIC_CONSISTENCY
}
OUTPUTS {
NORMALISED_PROCESSOR_ENTITIES
PROCESSOR_COMPONENT_RELATIONS
ISA_RELATIONS
MICROARCHITECTURE_RELATIONS
CORE_AND_THREAD_RELATIONS
CACHE_AND_MEMORY_RELATIONS
EXECUTION_RELATIONS
OPERATING_STATE_RELATIONS
FREQUENCY_AND_VOLTAGE_RELATIONS
POWER_RELATIONS
THERMAL_RELATIONS
EXECUTION_TRACES
PERFORMANCE_PROFILES
FAILURE_HYPOTHESES
BOTTLENECK_HYPOTHESES
CONFIDENCE_SCORES
EVIDENCE_LINKS
PROVENANCE_RECORDS
EXPLANATION_PATHS
}
UPDATE_MODEL {
ON PROCESSOR_OR_CONFIGURATION_CHANGE {
NORMALISE
ENTITY_RESOLUTION
UPDATE_CORE_TOPOLOGY
UPDATE_CACHE_HIERARCHY
UPDATE_EXECUTION_RESOURCES
UPDATE_POWER_AND_THERMAL_MODEL
UPDATE_CONFIGURATION
RECOMPUTE_AFFECTED_RELATIONS
UPDATE_CONFIDENCE
PRESERVE_VERSION_HISTORY
}
ON NEW_EXECUTION_PERFORMANCE_OR_SENSOR_DATA {
LINK_EVIDENCE
UPDATE_EXECUTION_PROFILE
UPDATE_OPERATING_STATE
UPDATE_POWER_AND_THERMAL_PROFILE
REASSESS_PERFORMANCE_RELATIONS
REASSESS_FAILURE_HYPOTHESES
UPDATE_CONFIDENCE
RECORD_PROVENANCE
}
ON ONTOLOGY_REVISION {
REMAP_TERMS
CHECK_SEMANTIC_EQUIVALENCE
IDENTIFY_DEPRECATED_TERMS
MIGRATE_RELATIONSHIPS
PRESERVE_PRIOR_VERSION_REFERENCES
}
}
FLOW_HASH {
HASH_INPUT =
CANONICALISE(
ENTITY_TYPES,
RELATIONSHIPS,
RULES,
CONFIDENCE,
SEMANTIC_EQUIVALENCE,
REASONING_CONSTRAINTS,
UPDATE_MODEL
)
FLOW_HASH = SHA256(HASH_INPUT)
}
AI_CONSUMPTION {
INDEX {
ONTOLOGY
ENTITY_TYPES
RELATIONSHIPS
RULES
OUTPUTS
}
RETRIEVE {
BY_PROCESSOR
BY_CORE
BY_THREAD
BY_ISA
BY_MICROARCHITECTURE
BY_EXECUTION_UNIT
BY_CACHE
BY_MEMORY_CONTROLLER
BY_FREQUENCY
BY_POWER
BY_TEMPERATURE
BY_PERFORMANCE
BY_FAILURE
BY_CONFIDENCE
}
REASON {
APPLY_RELATIONSHIPS
APPLY_RULES
TRACE_INSTRUCTION_EXECUTION
TRACE_CORE_AND_THREAD_TOPOLOGY
TRACE_CACHE_AND_MEMORY_ACCESS
ANALYSE_OPERATING_STATES
ANALYSE_FREQUENCY_AND_VOLTAGE
ANALYSE_POWER_AND_THERMAL_BEHAVIOUR
ANALYSE_PERFORMANCE
ANALYSE_FAILURES
CHECK_SEMANTIC_EQUIVALENCE
PRESERVE_UNCERTAINTY
TRACE_EVIDENCE
TRACE_PROVENANCE
GENERATE_EXPLANATION_PATH
}
RESPONSE_POLICY {
DISTINGUISH_PROCESSOR_FROM_CORE
DISTINGUISH_ISA_FROM_MICROARCHITECTURE
PRESERVE_WORKLOAD_MEMORY_AND_CONFIGURATION_CONTEXT
PRESERVE_POWER_AND_THERMAL_CONTEXT
DISTINGUISH_PEAK_FROM_SUSTAINED_PERFORMANCE
DISTINGUISH_FAILURE_SYMPTOM_FROM_ROOT_CAUSE
RETURN_CONFIDENCE_WHEN_AVAILABLE
RETURN_PROVENANCE_WHEN_AVAILABLE
AVOID_UNSUPPORTED_PROCESSOR_INFERENCE
}
}
TERMINAL {
RESULT =
VALIDATED(
SEMANTICALLY_NORMALISED(
EVIDENCE_LINKED(
CONFIDENCE_AWARE(
PROCESSOR_KNOWLEDGE
)
)
)
)
}
}
END FLOW
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