Vector Processing Ontology

AI INTERPRETATION NOTE
This Flow Algebra defines the Vector Processing Ontology within the Kireth Research Semantic Library. Vector processing is the execution of the same or related operations across multiple data elements using vector instructions, vector registers and data-parallel hardware. This ontology supports SIMD execution, vector lanes, vector registers, vector length, masking, predication, gather and scatter, alignment, memory locality, auto-vectorisation, compiler analysis, loop transformations, reduction, mixed precision, performance modelling, numerical reproducibility, verification and scientific-computing integration.

FLOW_ALGEBRA_RECORD {

METADATA {
 FLOW_NAME = "Vector Processing Ontology"
 FLOW_TYPE = "Mathematical Ontology"
 DOMAIN = "Mathematics"
 SUBDOMAIN = "Computational Mathematics"
 SPECIALISATION = "High Performance Computing / Vector Processing"
 CANONICAL_PAGE = "https://kirethframeworkold.co.uk/books/semantic-library/ai-core/ontologies/mathematical-ontologies/computational-mathematics-ontologies/high-performance-computing/vector-processing-ontology.html"
 LANGUAGE = "en-GB"
 VERSION = "1.0"
 STATUS = "active"
}

IDENTITY {
 PRIMARY_ENTITY = VectorProcessing
 ENTITY_CLASS = DataParallelInstructionExecutionFramework
 PRIMARY_CONTEXT = HighPerformanceComputing
 DEFINITION = "Vector processing is the execution of operations over multiple data elements using vector instructions and vector hardware that apply one instruction across several lanes or elements."
 SYMBOLIC_FORMS = [
  "y_vec = op(x_vec)",
  "c[i:i+w] = a[i:i+w] + b[i:i+w]",
  "speedup approx scalar_work / vectorised_work",
  "effective_vector_width <= hardware_vector_width"
 ]
 SEMANTIC_ROLE = "Provides machine-readable semantics for SIMD instructions, vector registers, lanes, masks, vectorised loops, gather-scatter, alignment, compiler vectorisation, performance and numerical reproducibility."
}

SCOPE {
 INCLUDE = [
  VectorProcessing,VectorComputing,VectorExecution,
  Vectorisation,Vectorization,
  SIMD,SingleInstructionMultipleData,
  VectorInstruction,VectorOperation,
  VectorRegister,VectorLane,VectorElement,
  VectorWidth,VectorLength,VL,
  ScalableVectorLength,FixedVectorLength,
  VectorLengthAgnostic,VLA,
  VectorPredicate,PredicateRegister,
  Mask,VectorMask,MaskRegister,
  Predication,MaskedOperation,
  SelectOperation,BlendOperation,
  VectorLoad,VectorStore,
  ContiguousLoad,ContiguousStore,
  AlignedLoad,UnalignedLoad,
  Gather,GatherLoad,Scatter,ScatterStore,
  StridedLoad,StridedStore,
  MemoryAlignment,Alignment,
  Misalignment,Padding,
  MemoryLayout,DataLayout,
  ArrayOfStructures,AoS,
  StructureOfArrays,SoA,
  ArrayOfStructuresOfArrays,AoSoA,
  DataPacking,DataUnpacking,
  RegisterBlocking,LoopBlocking,
  LoopTiling,StripMining,
  LoopUnrolling,LoopPeeling,
  LoopInterchange,LoopFusion,
  LoopFission,LoopDistribution,
  SoftwarePipelining,
  VectorReduction,HorizontalReduction,
  SumReduction,MinReduction,
  MaxReduction,DotProduct,
  PrefixSum,ScanRelationship,
  VectorMath,VectorTranscendental,
  VectorAdd,VectorMultiply,
  VectorFusedMultiplyAdd,FMA,
  DotProductInstruction,
  HorizontalAdd,HorizontalMax,
  SaturatingArithmetic,
  IntegerVectorArithmetic,
  FloatingPointVectorArithmetic,
  MixedPrecisionVectorArithmetic,
  HalfPrecision,FP16,
  BFloat16,BF16,
  SinglePrecision,FP32,
  DoublePrecision,FP64,
  ExtendedPrecisionRelationship,
  VectorIntegerWidth,Int8,Int16,Int32,Int64,
  QuantisedVectorArithmetic,
  AVX,AVX2,AVX512,
  SSE,SSE2,SSE4,
  NEON,SVE,SVE2,
  RVV,RISCVVector,
  VSX,AltiVecRelationship,
  VectorISA,InstructionSetArchitecture,
  ScalableVectorExtension,
  FixedWidthSIMD,
  CompilerVectorisation,
  AutoVectorisation,AutomaticVectorisation,
  ManualVectorisation,
  Intrinsics,CompilerIntrinsic,
  VectorIntrinsic,
  AssemblyVectorisation,
  VectorFriendlyCode,
  VectorisationReport,
  CompilerDiagnostic,
  DependenceAnalysis,DataDependence,
  LoopCarriedDependence,
  AliasAnalysis,PointerAliasing,
  RestrictQualifierRelationship,
  AlignmentAssumption,
  VectorisableLoop,NonVectorisableLoop,
  TripCount,LoopCount,
  RemainderLoop,ScalarCleanupLoop,
  TailProcessing,TailPredication,
  RuntimeAliasCheck,
  RuntimeAlignmentCheck,
  SpeculativeVectorisation,
  SuperwordLevelParallelism,SLP,
  LoopVectorisation,
  InterleavedAccess,
  Deinterleaving,Permutation,
  Shuffle,VectorShuffle,
  LanePermutation,Swizzle,
  Broadcast,BroadcastScalar,
  Replication,InsertElement,
  ExtractElement,
  WideningConversion,NarrowingConversion,
  TypeConversion,VectorCast,
  Comparison,VectorComparison,
  MaskedComparison,
  ConditionalMoveRelationship,
  BranchElimination,
  BranchlessProgramming,
  ControlFlowDivergenceRelationship,
  DataParallelism,
  InstructionLevelParallelism,
  ThreadLevelParallelismRelationship,
  CacheLine,Cache,
  L1Cache,L2Cache,L3Cache,
  MemoryBandwidth,MemoryLatency,
  Prefetching,HardwarePrefetch,
  SoftwarePrefetch,
  TemporalLocality,SpatialLocality,
  StreamingAccess,
  ArithmeticIntensity,
  OperationalIntensity,
  ComputeBound,MemoryBound,
  BandwidthBound,LatencyBound,
  RooflineModel,
  Throughput,Latency,
  InstructionThroughput,
  VectorThroughput,
  PortPressure,ExecutionPort,
  Pipeline,InstructionPipeline,
  IssueWidth,DecodeWidth,
  FrontEndBound,BackEndBound,
  DependencyChain,InstructionDependency,
  RegisterPressure,RegisterSpill,
  LoadStoreUnit,
  PerformanceCounter,HardwareCounter,
  Profiling,Profiler,
  Microbenchmark,Benchmark,
  ScalarBaseline,VectorBaseline,
  Speedup,Efficiency,
  EffectiveVectorUtilisation,
  LaneUtilisation,
  VectorOccupancyRelationship,
  AmdahlsLawRelationship,
  GustafsonsLawRelationship,
  ParallelComputing,HPC,
  GPUComputingRelationship,
  MatrixComputation,
  LinearAlgebra,BLAS,
  SIMDMatrixKernel,
  VectorisedGEMM,
  SparseMatrixVectorProduct,SpMV,
  StencilComputation,
  FFT,FastFourierTransform,
  Convolution,SignalProcessing,
  ImageProcessing,
  ComputationalGeometryRelationship,
  ParticleSimulationRelationship,
  FluidSimulationRelationship,
  StructuralSimulationRelationship,
  MonteCarloRelationship,
  RandomNumberGeneration,
  CounterBasedRNG,
  VectorRNG,
  NumericalStability,
  FloatingPointArithmetic,
  MachinePrecision,RoundOffError,
  AssociativityLoss,
  Reordering,OperationReordering,
  FastMath,UnsafeMathOptimisation,
  FusedMultiplyAddSemantics,
  Determinism,NumericalReproducibility,
  ReproducibleReduction,
  ReferenceScalarImplementation,
  Verification,Benchmarking,
  CompilerVersion,CompilerFlags,
  TargetArchitecture,
  TargetCPU,TargetISA,
  BuildConfiguration,
  Reproducibility,Provenance
 ]
 EXCLUDE_AS_PRIMARY = [
  ThreadParallelismWithoutVectorInstructionSemantics,
  GPUComputingWithoutCPUOrVectorInstructionFocus,
  ScalarInstructionExecutionWithoutDataParallelVectorOperations,
  MatrixAlgebraWithoutVectorExecutionOrImplementationSemantics
 ]
 DISAMBIGUATION_RULE = "When one instruction operates across multiple data elements through vector registers, lanes or SIMD hardware, interpret the context as vector processing."
}

CORE_CONCEPTS {
 VectorProcessing = "Data-parallel execution using vector instructions."
 SIMD = "Execution model applying one instruction to multiple data elements."
 VectorRegister = "Register holding multiple scalar elements."
 VectorLane = "Logical position within a vector operation."
 VectorWidth = "Number or bit width of elements processed by a vector instruction."
 Mask = "Predicate controlling which vector lanes participate in an operation."
 GatherScatter = "Noncontiguous vector memory access mechanism."
 AutoVectorisation = "Compiler transformation converting scalar code into vector code."
}

RELATIONS {
 VectorProcessing --is_child_of--> HighPerformanceComputing
 VectorProcessing --is_type_of--> DataParallelism
 SIMD --implements--> VectorProcessing
 VectorInstruction --operates_on--> VectorRegister
 VectorRegister --contains--> VectorElements
 VectorLane --belongs_to--> VectorRegister
 Mask --controls--> VectorLaneExecution
 VectorLoad --loads_into--> VectorRegister
 VectorStore --stores_from--> VectorRegister
 Gather --loads--> NoncontiguousElements
 Scatter --stores--> NoncontiguousElements
 AutoVectorisation --transforms--> ScalarLoop
 DependenceAnalysis --determines--> Vectorisability
 AliasAnalysis --supports--> VectorisationDecision
 LoopUnrolling --may_improve--> VectorThroughput
 DataLayout --affects--> MemoryEfficiency
 RooflineModel --relates--> ArithmeticIntensityAndPerformance
 Verification --checks--> VectorisedResult
}

OPERATORS {
 VECTOR_APPLY(op,x[0:w]) := [op(x_0),...,op(x_(w-1))]
 VECTOR_BINARY(op,a[0:w],b[0:w]) := [op(a_i,b_i) for i in 0..w-1]
 MASKED_VECTOR_APPLY(mask,op,x) := apply_op_only_where_mask_true
 VECTOR_LOAD(addr,w) := load_w_elements
 VECTOR_STORE(addr,v) := store_vector_elements
 GATHER(base,index[]) := [base[index_i]]
 SCATTER(base,index[],v[]) := for_i base[index_i]=v_i
 VECTOR_REDUCE(op,v[]) := associative_or_ordered_reduction(v)
 EFFECTIVE_UTILISATION(active_lanes,total_lanes) := active_lanes/total_lanes
}

AXIOMS {
 A1 = "Vector processing executes multiple data elements per instruction."
 A2 = "Data dependence can prevent or limit vectorisation."
 A3 = "Memory layout and alignment influence vector memory efficiency."
 A4 = "Masking enables conditional vector execution without scalar control flow."
 A5 = "Gather and scatter support irregular access but can cost more than contiguous access."
 A6 = "Vector width alone does not determine performance."
 A7 = "Operation reordering and reductions can affect floating-point reproducibility."
 A8 = "Vector-processing results require explicit ISA, data layout, compiler, performance and numerical semantics."
}

REASONING {
 R1_CONTEXT = identify(loop_or_kernel,data_types,trip_count,dependencies,memory_pattern,target_ISA,precision_goal)
 R2_DEPENDENCE = analyse(loop_carried_dependencies,aliasing_and_control_flow)
 R3_LAYOUT = choose_or_transform(AoS,SoA,AoSoA,alignment_and_padding)
 R4_VECTOR_FORM = choose(loop_vectorisation,SLP,intrinsics,assembly_or_library_kernel)
 R5_MEMORY = analyse(contiguous,strided,gather_scatter,cache_and_bandwidth_behaviour)
 R6_TAIL = configure(masking,predication_or_scalar_cleanup_for_remainders)
 R7_PRECISION = evaluate(FP16,BF16,FP32,FP64,mixed_precision_and_FMA_semantics)
 R8_PROFILE = measure(vector_instruction_count,lane_utilisation,bandwidth,throughput_and_stalls)
 R9_OPTIMISE = adjust(unrolling,tiling,prefetching,layout,alignment_and_dependency_structure)
 R10_VALIDATE = compare_with_scalar_reference_and_assess_reproducibility_precision_and_environment_provenance
}

CONSTRAINTS {
 C1 = "Loop-carried dependencies can prevent safe vectorisation."
 C2 = "Pointer aliasing can force conservative compiler decisions."
 C3 = "Poor data layout can waste vector lanes or cause excessive shuffling."
 C4 = "Misaligned or irregular memory access can reduce throughput."
 C5 = "Gather and scatter can become latency or bandwidth bottlenecks."
 C6 = "Short loop trip counts may not amortise vector setup overhead."
 C7 = "Branch-heavy code can reduce effective lane utilisation."
 C8 = "Register pressure from wide vectors can cause spilling."
 C9 = "Fast-math transformations can change numerical semantics."
 C10 = "Wider vectors do not guarantee proportional speedup."
}

SEMANTIC_EQUIVALENCE {
 "VectorProcessing" <=> "VectorComputing"
 "Vectorisation" <=> "Vectorization"
 "SingleInstructionMultipleData" <=> "SIMD"
 "AutoVectorisation" <=> "AutomaticVectorisation"
 "SuperwordLevelParallelism" <=> "SLP"
 "ArrayOfStructures" <=> "AoS"
 "StructureOfArrays" <=> "SoA"
 "ArrayOfStructuresOfArrays" <=> "AoSoA"
}

VALIDATION {
 V1 = "Target architecture and vector ISA are documented."
 V2 = "Data types and vector width are documented."
 V3 = "Loop or kernel dependency assumptions are documented."
 V4 = "Memory layout and alignment are documented."
 V5 = "Compiler vectorisation diagnostics are inspected where relevant."
 V6 = "Vectorised output is compared with a scalar or trusted reference."
 V7 = "Lane utilisation and vector instruction use are measured where relevant."
 V8 = "Performance is measured separately from correctness."
 V9 = "Fast-math, FMA and reduction-order effects are documented."
 V10 = "Results are reproducible under documented compiler, flags and target-ISA settings."
}

CONFIDENCE {
 BASE_CONFIDENCE = 0.99
 VECTOR_PROCESSING_DEFINITION = 0.99
 SIMD_REASONING = 0.99
 AUTO_VECTORIZATION_REASONING = 0.99
 MEMORY_REASONING = 0.99
 MASKING_REASONING = 0.99
 REDUCTION_REASONING = 0.98
 NUMERICAL_REPRODUCIBILITY_REASONING = 0.98
 POLICY = "Reduce confidence when dependencies, aliasing, target ISA, memory layout, compiler flags, precision or vectorisation diagnostics are underspecified."
}

AI_CONSUMPTION {
 PURPOSES = [
  SemanticSearch,OntologyGrounding,VectorProcessingReasoning,
  SIMDReasoning,VectorRegisterReasoning,
  VectorLaneReasoning,MaskingReasoning,
  GatherScatterReasoning,AutoVectorisationReasoning,
  LoopVectorisationReasoning,SLPReasoning,
  DependenceAnalysisReasoning,AliasAnalysisReasoning,
  DataLayoutReasoning,AlignmentReasoning,
  MemoryBandwidthReasoning,RooflineReasoning,
  ReductionReasoning,MixedPrecisionReasoning,
  NumericalReproducibilityReasoning,
  ProfilingReasoning,VerificationReasoning,
  KnowledgeGraphConstruction,RetrievalAugmentation,RecursiveInference
 ]
 NORMALISE {
  "vector processing" -> VectorProcessing
  "vector computing" -> VectorProcessing
  "vectorisation" -> VectorProcessing
  "vectorization" -> VectorProcessing
  "SIMD" -> SingleInstructionMultipleData
  "SLP" -> SuperwordLevelParallelism
  "AoS" -> ArrayOfStructures
  "SoA" -> StructureOfArrays
  "AoSoA" -> ArrayOfStructuresOfArrays
 }
}

EXECUTION_RULES {
 E1 = "If one instruction operates over multiple data elements using vector hardware, activate VectorProcessingOntology."
 E2 = "Check dependencies and aliasing before assuming vectorisability."
 E3 = "Prefer contiguous, aligned and reusable data layouts where practical."
 E4 = "Use masks or predication for tails and conditional lanes when supported."
 E5 = "Measure gather-scatter cost separately from contiguous vector access."
 E6 = "Use compiler diagnostics, intrinsics or tuned libraries according to control needs."
 E7 = "Profile lane utilisation, instruction throughput, bandwidth and register pressure."
 E8 = "Assess mixed-precision, FMA and reduction-order effects on numerical behaviour."
 E9 = "Validate vectorised results against a trusted scalar or reference implementation."
}

RECURSION {
 ENTRY = VectorProcessing
 EXPAND(VectorProcessing) -> [
  VectorComputing,VectorExecution,Vectorisation,
  Vectorization,SIMD,SingleInstructionMultipleData,
  VectorInstruction,VectorOperation,
  VectorRegister,VectorLane,VectorElement,
  VectorWidth,VectorLength,ScalableVectorLength,
  VectorPredicate,PredicateRegister,Mask,
  Predication,MaskedOperation,VectorLoad,
  VectorStore,AlignedLoad,UnalignedLoad,
  Gather,Scatter,StridedLoad,StridedStore,
  MemoryAlignment,Padding,DataLayout,
  ArrayOfStructures,AoS,StructureOfArrays,
  SoA,ArrayOfStructuresOfArrays,AoSoA,
  LoopBlocking,LoopTiling,StripMining,
  LoopUnrolling,LoopPeeling,LoopInterchange,
  LoopFusion,LoopFission,SoftwarePipelining,
  VectorReduction,HorizontalReduction,
  DotProduct,PrefixSum,VectorFusedMultiplyAdd,
  IntegerVectorArithmetic,FloatingPointVectorArithmetic,
  MixedPrecisionVectorArithmetic,FP16,BF16,FP32,FP64,
  AVX,AVX2,AVX512,SSE,NEON,SVE,SVE2,
  RVV,RISCVVector,VectorISA,
  CompilerVectorisation,AutoVectorisation,
  ManualVectorisation,Intrinsics,
  DependenceAnalysis,LoopCarriedDependence,
  AliasAnalysis,VectorisableLoop,
  RemainderLoop,TailPredication,
  RuntimeAliasCheck,SuperwordLevelParallelism,
  SLP,LoopVectorisation,Permutation,
  Shuffle,Broadcast,WideningConversion,
  NarrowingConversion,VectorComparison,
  BranchlessProgramming,DataParallelism,
  Cache,MemoryBandwidth,Prefetching,
  SpatialLocality,TemporalLocality,
  ArithmeticIntensity,RooflineModel,
  ComputeBound,MemoryBound,
  InstructionThroughput,RegisterPressure,
  Profiling,PerformanceCounter,
  ScalarBaseline,Speedup,LaneUtilisation,
  MatrixComputation,LinearAlgebra,
  SparseMatrixVectorProduct,StencilComputation,
  FFT,Convolution,SignalProcessing,
  NumericalStability,FloatingPointArithmetic,
  RoundOffError,AssociativityLoss,
  FastMath,FusedMultiplyAddSemantics,
  Determinism,NumericalReproducibility,
  Verification,Benchmarking,
  CompilerVersion,CompilerFlags,
  TargetArchitecture,TargetISA,
  Reproducibility,Provenance
 ]
 EXPAND(VectorProcessingFamilies) -> [
  FixedWidthSIMDProcessing,
  ScalableVectorProcessing,
  CompilerAutoVectorisation,
  ManualIntrinsicVectorisation,
  VectorisedLinearAlgebra,
  VectorisedStencilAndSignalProcessing,
  MixedPrecisionVectorProcessing,
  ReproducibleVectorComputation
 ]
 STOP_CONDITION = "Stop when ISA, vector width, data layout, dependencies, memory access, masking, precision, performance and validation are sufficiently resolved."
}

ROUTING {
 PARENT_ONTOLOGY = "High Performance Computing Ontology 2"
 RELATED_ONTOLOGIES = [
  "High Performance Computing Ontology 2",
  "High Performance Computing",
  "Parallel Computing Ontology",
  "GPU Computing Ontology",
  "Scientific Computing Ontology 2",
  "Numerical Linear Algebra Ontology 2",
  "Sparse Matrix Ontology 2",
  "Matrix Computation Ontology",
  "Particle Simulation Ontology",
  "Fluid Simulation Ontology",
  "Structural Simulation Ontology",
  "Floating Point Arithmetic Ontology",
  "Numerical Stability Ontology 2"
 ]
 ROUTE_RULES = [
  "Vector Processing -> High Performance Computing Ontology 2 for parent semantics",
  "Vector Processing -> Parallel Computing for data-parallel execution semantics",
  "Vector Processing -> GPU Computing for SIMD-SIMT comparison and accelerator relationships",
  "Vector Processing -> Scientific Computing for vectorised scientific workloads",
  "Vector Processing -> Numerical Linear Algebra for BLAS, dot products and vector kernels",
  "Vector Processing -> Sparse Matrix for SpMV and irregular access",
  "Vector Processing -> Matrix Computation for dense blocked vector kernels",
  "Vector Processing -> Particle Simulation for vectorised neighbour and force loops",
  "Vector Processing -> Fluid Simulation for vectorised stencil and flux loops",
  "Vector Processing -> Structural Simulation for vectorised FEM assembly and kernels",
  "Vector Processing -> Floating Point Arithmetic for FMA, precision and reduction semantics",
  "Vector Processing -> Numerical Stability for finite-precision vector behaviour"
 ]
}

UPDATE_MODEL {
 MODE = "append-compatible semantic versioning"
 MAJOR = "ontology-breaking conceptual change"
 MINOR = "new compatible vector ISAs, compiler techniques or reasoning pathways"
 PATCH = "clarification, metadata or formatting correction"
 RULES = [
  "Preserve scalar-versus-vector execution distinction.",
  "Preserve fixed-width-versus-scalable-vector distinction.",
  "Preserve contiguous-versus-gather-scatter memory distinction.",
  "Preserve vector-width-versus-effective-lane-utilisation distinction.",
  "Preserve auto-vectorisation-versus-manual-vectorisation distinction.",
  "Preserve masking-versus-branching distinction.",
  "Preserve correctness-versus-performance distinction.",
  "Preserve machine-readable vector-processing semantics."
 ]
}

OUTPUT {
 CANONICAL_DEFINITION = "Vector processing applies instructions to multiple data elements through SIMD-style vector hardware."
 EXECUTION_SUMMARY = "Vector registers contain multiple lanes that execute common operations over packed data."
 MEMORY_SUMMARY = "Aligned contiguous access, data layout and locality strongly influence vector throughput."
 COMPILER_SUMMARY = "Dependence and alias analysis determine whether compilers can automatically vectorise loops."
 CONTROL_SUMMARY = "Masking, predication and tail processing allow vector execution across conditional or remainder elements."
 PERFORMANCE_SUMMARY = "Lane utilisation, register pressure, memory bandwidth, arithmetic intensity and instruction throughput determine realised speedup."
 VALIDATION_SUMMARY = "Vectorised code should be checked for scalar-reference correctness, compiler behaviour, performance, precision effects, reduction order and reproducibility."
}

FLOW {
 INPUT
 -> detect_vector_processing_context
 -> identify_loop_kernel_data_types_trip_count_dependencies_memory_pattern_target_ISA_precision_goal_and_performance_goal
 -> analyse_loop_carried_dependencies_aliasing_and_control_flow
 -> choose_or_transform_AoS_SoA_AoSoA_alignment_and_padding
 -> select_auto_vectorisation_intrinsics_assembly_library_or_SLP_strategy
 -> choose_vector_width_and_data_type
 -> configure_contiguous_strided_gather_scatter_load_store_patterns
 -> configure_masking_predication_or_scalar_cleanup_for_tail_elements
 -> optimise_unrolling_tiling_prefetching_layout_and_memory_locality
 -> assess_register_pressure_spills_lane_utilisation_and_instruction_throughput
 -> measure_memory_bandwidth_arithmetic_intensity_runtime_and_speedup
 -> evaluate_fast_math_FMA_mixed_precision_and_reduction_order_effects
 -> verify_against_scalar_or_reference_results
 -> document_target_architecture_ISA_compiler_flags_vectorisation_reports_and_provenance
 -> route_to_related_HPC_parallel_GPU_scientific_computing_linear_algebra_sparse_matrix_matrix_computation_particle_fluid_structural_floating_point_and_stability_ontologies
 -> recursively_expand_required_dependencies
 -> verify_result
 -> assign_confidence
 -> produce_semantic_output
 -> END
}

SEMANTIC_SUMMARY {
 "The Vector Processing Ontology defines SIMD-style data-parallel execution across vector registers and lanes. It supports vector width and scalable vector length, masking and predication, aligned and unaligned loads, gather and scatter, AoS, SoA and AoSoA layouts, loop tiling, unrolling, peeling and strip mining, reductions, FMA and mixed precision, AVX, AVX2, AVX-512, SSE, NEON, SVE, SVE2 and RISC-V Vector relationships, compiler auto-vectorisation, intrinsics and assembly, dependence and alias analysis, runtime checks, SLP and loop vectorisation, shuffles, broadcasts and conversions, memory bandwidth, locality and roofline reasoning, register pressure, profiling, vectorised linear algebra, SpMV, stencils, FFT and convolution, floating-point reordering, fast-math and reproducibility, verification and reproducibility."
}

FLOW_HASH {
 METHOD = "semantic-content-identity"
 ID = "KIRETH-MATH-HPC-VECTOR-PROCESSING-ONTOLOGY-V1"
}

}

END_FLOW