Microarchitecture Ontology

AI SEARCH

FLOW ALGEBRA — MICROARCHITECTURE ONTOLOGY
Semantic Library
Version: 4.0
Canonical Page:
https://kirethresearch.org/booksai-core/ontologies/computing-ontologies/computer-architecture/microarchitecture-ontology.html

FLOW MICROARCHITECTURE_ONTOLOGY {

  META {
    DOMAIN = "Computing Ontologies"
    SUBDOMAIN = "Computer Architecture"
    ONTOLOGY = "Microarchitecture Ontology"
    PURPOSE = "Formalise processor implementation structures, pipelines, execution units, caches, scheduling, speculation and internal state used to implement an instruction set architecture."
    LOCALE = "en-GB"
  }

  ENTITY_TYPES {
    MICROARCHITECTURE
    INSTRUCTION_SET_ARCHITECTURE
    ISA
    PROCESSOR
    CPU
    CORE
    FRONT_END
    BACK_END
    FETCH_UNIT
    DECODE_UNIT
    DISPATCH_UNIT
    ISSUE_UNIT
    SCHEDULER
    EXECUTION_UNIT
    INTEGER_UNIT
    FLOATING_POINT_UNIT
    VECTOR_UNIT
    LOAD_STORE_UNIT
    BRANCH_UNIT
    RETIREMENT_UNIT
    REORDER_BUFFER
    RESERVATION_STATION
    REGISTER_FILE
    PHYSICAL_REGISTER
    ARCHITECTURAL_REGISTER
    REGISTER_RENAMING
    PIPELINE
    PIPELINE_STAGE
    INSTRUCTION
    MICRO_OPERATION
    UOP
    CACHE
    L1_CACHE
    L2_CACHE
    L3_CACHE
    TLB
    MEMORY_QUEUE
    LOAD_QUEUE
    STORE_QUEUE
    BRANCH_PREDICTOR
    BRANCH_TARGET_BUFFER
    RETURN_ADDRESS_STACK
    PREFETCHER
    INTERCONNECT
    CLOCK
    CLOCK_CYCLE
    SPECULATION
    OUT_OF_ORDER_EXECUTION
    IN_ORDER_EXECUTION
    DEPENDENCY
    DATA_DEPENDENCY
    CONTROL_DEPENDENCY
    HAZARD
    STALL
    FLUSH
    STATE
    MICROARCHITECTURAL_STATE
    ARCHITECTURAL_STATE
    LATENCY
    THROUGHPUT
    BANDWIDTH
    POWER
    TEMPERATURE
    CONFIGURATION
    VERSION
    PERFORMANCE_METRIC
    EVIDENCE
    CONFIDENCE_SCORE
    PROVENANCE_RECORD
  }

  RELATIONSHIPS {
    IS_A
    INSTANCE_OF
    PART_OF
    CONTAINS
    IMPLEMENTS
    HAS_PIPELINE
    HAS_STAGE
    HAS_UNIT
    HAS_CACHE
    HAS_PREDICTOR
    HAS_REGISTER_FILE
    FETCHES
    DECODES
    RENAMES
    DISPATCHES
    ISSUES
    SCHEDULES
    EXECUTES
    LOADS
    STORES
    RETIRES
    COMMITS
    PREDICTS
    SPECULATES
    PREFETCHES
    DEPENDS_ON
    HAS_DEPENDENCY
    STALLS
    FLUSHES
    FORWARDS_TO
    READS
    WRITES
    HAS_STATE
    TRANSITIONS_TO
    HAS_LATENCY
    HAS_THROUGHPUT
    HAS_BANDWIDTH
    HAS_POWER
    HAS_TEMPERATURE
    HAS_CONFIGURATION
    HAS_VERSION
    PRECEDES
    FOLLOWS
    DERIVED_FROM
    INFERRED_FROM
    HAS_EVIDENCE
    HAS_CONFIDENCE
    HAS_PROVENANCE
    MAPS_TO
    SEMANTICALLY_EQUIVALENT_TO
  }

  INPUTS {
    MICROARCHITECTURE_SPECIFICATIONS
    ISA_DEFINITIONS
    PIPELINE_DEFINITIONS
    EXECUTION_UNIT_DEFINITIONS
    CACHE_CONFIGURATIONS
    REGISTER_RENAMING_DEFINITIONS
    SCHEDULER_DEFINITIONS
    BRANCH_PREDICTOR_DEFINITIONS
    PREFETCHER_DEFINITIONS
    MEMORY_SYSTEM_DEFINITIONS
    EXECUTION_TRACES
    PERFORMANCE_COUNTERS
    POWER_METRICS
    TEMPERATURE_METRICS
    CONFIGURATION_DATA
    VERSION_DATA
    ONTOLOGY_TERMS
  }

  NORMALISE {
    STANDARDISE_IDENTIFIERS
    NORMALISE_MICROARCHITECTURE_NAMES
    NORMALISE_PIPELINE_STAGE_NAMES
    NORMALISE_EXECUTION_UNIT_NAMES
    NORMALISE_CACHE_UNITS
    NORMALISE_LATENCY_UNITS
    NORMALISE_BANDWIDTH_UNITS
    NORMALISE_POWER_UNITS
    NORMALISE_TEMPERATURE_UNITS
    NORMALISE_VERSION_IDENTIFIERS
    RESOLVE_COMPONENT_IDENTITIES
    ALIGN_ONTOLOGY_TERMS
    REMOVE_DUPLICATES
    VALIDATE_METADATA
    PRESERVE_PROVENANCE
  }

  PROCESS MICROARCHITECTURE_PIPELINE {
    INSTRUCTION_STREAM
      -> FETCH
      -> DECODE
      -> MICRO_OPERATION_GENERATION_IF_REQUIRED
      -> REGISTER_RENAME_IF_APPLICABLE
      -> DISPATCH
      -> SCHEDULE
      -> ISSUE
      -> EXECUTE
      -> MEMORY_ACCESS_IF_REQUIRED
      -> WRITEBACK
      -> RETIRE_OR_COMMIT
  }

  PROCESS OUT_OF_ORDER_REASONING {
    DECODED_OPERATIONS
      -> REGISTER_RENAMING

    REGISTER_RENAMING
      -> DEPENDENCY_TRACKING

    DEPENDENCY_TRACKING
      -> SCHEDULER_QUEUE

    READY_OPERATIONS
      -> ISSUE

    ISSUE
      -> EXECUTION

    EXECUTION
      -> RESULT_COMPLETION

    RESULT_COMPLETION
      -> REORDER_BUFFER

    REORDER_BUFFER
      -> IN_ORDER_RETIREMENT
  }

  PROCESS BRANCH_PREDICTION_REASONING {
    BRANCH_INSTRUCTION
      -> PREDICTOR_LOOKUP

    PREDICTOR_LOOKUP
      -> PREDICTED_DIRECTION
      -> PREDICTED_TARGET

    PREDICTED_PATH
      -> SPECULATIVE_FETCH_AND_EXECUTION

    ACTUAL_BRANCH_RESULT
      -> PREDICTION_CHECK

    MISPREDICTION
      -> SQUASH_OR_FLUSH
      -> CORRECT_PATH_RESTART
  }

  PROCESS CACHE_REASONING {
    MEMORY_OPERATION
      -> L1_LOOKUP

    L1_LOOKUP
      -> HIT_OR_MISS

    MISS
      -> NEXT_CACHE_LEVEL_OR_MEMORY

    DATA_RETURN
      -> CACHE_FILL_IF_REQUIRED
      -> LOAD_STORE_UNIT
  }

  PROCESS HAZARD_REASONING {
    PIPELINE_STATE
      -> DATA_HAZARD_CHECK
      -> CONTROL_HAZARD_CHECK
      -> STRUCTURAL_HAZARD_CHECK

    HAZARD
      -> FORWARD_OR_STALL_OR_RESCHEDULE_OR_FLUSH

    RESOLUTION
      -> NEXT_PIPELINE_STATE
  }

  PROCESS PERFORMANCE_REASONING {
    MICROARCHITECTURE + WORKLOAD + CONFIGURATION
      -> EXECUTION_PROFILE

    EXECUTION_PROFILE
      -> IPC_ANALYSIS
      -> PIPELINE_UTILISATION
      -> CACHE_BEHAVIOUR
      -> BRANCH_BEHAVIOUR
      -> EXECUTION_UNIT_UTILISATION
      -> MEMORY_STALL_ANALYSIS
      -> POWER_AND_THERMAL_ANALYSIS

    EXECUTION_PROFILE
      -> BOTTLENECK_HYPOTHESIS
  }

  RULES {
    IF MICROARCHITECTURE IMPLEMENTS ISA
    THEN PRESERVE DISTINCTION(MICROARCHITECTURE, ISA)

    IF INSTRUCTION_IS_DECOMPOSED
    THEN LINK MACHINE_INSTRUCTION TO MICRO_OPERATIONS

    IF SPECULATIVE_EXECUTION_OCCURS
    THEN DISTINGUISH SPECULATIVE_STATE FROM COMMITTED_ARCHITECTURAL_STATE

    IF REGISTER_RENAMING_OCCURS
    THEN DISTINGUISH ARCHITECTURAL_REGISTER FROM PHYSICAL_REGISTER

    IF OUT_OF_ORDER_EXECUTION_OCCURS
    THEN DO_NOT_INFER_OUT_OF_ORDER_ARCHITECTURAL_COMMIT

    IF CACHE_MISS_OCCURS
    THEN TRACE_REQUEST_TO_NEXT_MEMORY_LEVEL

    IF TWO_PROCESSORS_IMPLEMENT_SAME_ISA
    THEN DO_NOT_ASSUME_IDENTICAL_MICROARCHITECTURE

    IF SEMANTIC_IDENTIFIERS_DIFFER
    AND MICROARCHITECTURAL_REFERENT_IS_SAME
    THEN APPLY SEMANTIC_EQUIVALENCE
  }

  CONFIDENCE {
    CONFIDENCE_SCORE =
      WEIGHT(
        SPECIFICATION_COMPLETENESS,
        ISA_MAPPING_CERTAINTY,
        COMPONENT_RESOLUTION,
        PIPELINE_MODEL_CERTAINTY,
        TRACE_COMPLETENESS,
        PERFORMANCE_COUNTER_QUALITY,
        MEASUREMENT_REPRODUCIBILITY,
        PROVENANCE_COMPLETENESS
      )

    LEVELS {
      HIGH
      MODERATE
      LOW
      INSUFFICIENT
    }

    IF INTERNAL_IMPLEMENTATION_DETAILS_ARE_UNKNOWN
    THEN REDUCE_INTERNAL_INFERENCE_CONFIDENCE

    IF WORKLOAD_OR_CONFIGURATION_IS_UNKNOWN
    THEN REDUCE_PERFORMANCE_INFERENCE_CONFIDENCE

    IF REPRODUCIBLE_TRACES_CONFIRM_BEHAVIOUR
    THEN INCREASE CONFIDENCE_SCORE
  }

  SEMANTIC_EQUIVALENCE {
    EQUIVALENCE_KEY =
      NORMALISE(
        ENTITY_TYPE,
        CANONICAL_IDENTIFIER,
        ISA,
        MICROARCHITECTURE_VERSION,
        CONFIGURATION,
        IMPLEMENTATION_CONTEXT
      )

    IF EQUIVALENCE_KEY(A) == EQUIVALENCE_KEY(B)
    THEN A SEMANTICALLY_EQUIVALENT_TO B

    ELSE PRESERVE_DISTINCT_ENTITIES
  }

  REASONING_CONSTRAINTS {
    ISA != MICROARCHITECTURE
    ARCHITECTURAL_REGISTER != PHYSICAL_REGISTER
    MACHINE_INSTRUCTION != MICRO_OPERATION
    SPECULATIVE_STATE != COMMITTED_STATE
    EXECUTION_COMPLETION != ARCHITECTURAL_RETIREMENT
    OUT_OF_ORDER_EXECUTION != OUT_OF_ORDER_COMMIT
    CACHE_HIT_RATE_IS_WORKLOAD_DEPENDENT
    BRANCH_ACCURACY_IS_WORKLOAD_DEPENDENT
    IPC_IS_WORKLOAD_DEPENDENT
    CLOCK_RATE != OVERALL_PERFORMANCE
    MICROARCHITECTURAL_STATE_MAY_NOT_BE_ARCHITECTURALLY_VISIBLE
    POWER_AND_THERMAL_LIMITS_AFFECT_SUSTAINED_BEHAVIOUR
    CONFIGURATION_AFFECTS_PERFORMANCE
    PROVENANCE_MUST_BE_PRESERVED
    UNCERTAINTY_MUST_NOT_BE_DISCARDED
  }

  VALIDATION {
    CHECK_ENTITY_TYPES
    CHECK_RELATION_DOMAINS_AND_RANGES
    CHECK_MICROARCHITECTURE_IDENTIFIER
    CHECK_ISA_MAPPING
    CHECK_PIPELINE_MODEL
    CHECK_EXECUTION_UNITS
    CHECK_REGISTER_RENAMING
    CHECK_SCHEDULER_MODEL
    CHECK_REORDER_BUFFER
    CHECK_BRANCH_PREDICTOR
    CHECK_CACHE_HIERARCHY
    CHECK_SPECULATION_STATE
    CHECK_EXECUTION_TRACE
    CHECK_PERFORMANCE_CONTEXT
    CHECK_POWER_AND_THERMAL_CONTEXT
    CHECK_CONFIGURATION
    CHECK_VERSION_CONTEXT
    CHECK_PROVENANCE
    CHECK_CONFIDENCE
    CHECK_SEMANTIC_CONSISTENCY
  }

  OUTPUTS {
    NORMALISED_MICROARCHITECTURE_ENTITIES
    ISA_IMPLEMENTATION_RELATIONS
    PIPELINE_RELATIONS
    EXECUTION_UNIT_RELATIONS
    MICRO_OPERATION_RELATIONS
    REGISTER_RENAMING_RELATIONS
    SCHEDULING_RELATIONS
    SPECULATION_RELATIONS
    BRANCH_PREDICTION_RELATIONS
    CACHE_RELATIONS
    MICROARCHITECTURAL_STATE_TRANSITIONS
    EXECUTION_TRACES
    PERFORMANCE_PROFILES
    POWER_AND_THERMAL_PROFILES
    BOTTLENECK_HYPOTHESES
    CONFIDENCE_SCORES
    EVIDENCE_LINKS
    PROVENANCE_RECORDS
    EXPLANATION_PATHS
  }

  UPDATE_MODEL {
    ON MICROARCHITECTURE_OR_CONFIGURATION_CHANGE {
      NORMALISE
      ENTITY_RESOLUTION
      UPDATE_PIPELINE_MODEL
      UPDATE_EXECUTION_UNITS
      UPDATE_CACHE_CONFIGURATION
      UPDATE_PREDICTOR_MODEL
      UPDATE_SCHEDULER_MODEL
      RECOMPUTE_AFFECTED_RELATIONS
      UPDATE_CONFIDENCE
      PRESERVE_VERSION_HISTORY
    }

    ON NEW_EXECUTION_OR_PERFORMANCE_DATA {
      LINK_EVIDENCE
      UPDATE_EXECUTION_PROFILE
      UPDATE_CACHE_PROFILE
      UPDATE_BRANCH_PROFILE
      UPDATE_POWER_AND_THERMAL_PROFILE
      REASSESS_BOTTLENECKS
      UPDATE_CONFIDENCE
      RECORD_PROVENANCE
    }

    ON ONTOLOGY_REVISION {
      REMAP_TERMS
      CHECK_SEMANTIC_EQUIVALENCE
      IDENTIFY_DEPRECATED_TERMS
      MIGRATE_RELATIONSHIPS
      PRESERVE_PRIOR_VERSION_REFERENCES
    }
  }

  FLOW_HASH {
    HASH_INPUT =
      CANONICALISE(
        ENTITY_TYPES,
        RELATIONSHIPS,
        RULES,
        CONFIDENCE,
        SEMANTIC_EQUIVALENCE,
        REASONING_CONSTRAINTS,
        UPDATE_MODEL
      )

    FLOW_HASH = SHA256(HASH_INPUT)
  }

  AI_CONSUMPTION {
    INDEX {
      ONTOLOGY
      ENTITY_TYPES
      RELATIONSHIPS
      RULES
      OUTPUTS
    }

    RETRIEVE {
      BY_MICROARCHITECTURE
      BY_ISA
      BY_PIPELINE
      BY_EXECUTION_UNIT
      BY_MICRO_OPERATION
      BY_REGISTER_RENAMING
      BY_SCHEDULER
      BY_BRANCH_PREDICTOR
      BY_CACHE
      BY_SPECULATION
      BY_PERFORMANCE
      BY_CONFIDENCE
    }

    REASON {
      APPLY_RELATIONSHIPS
      APPLY_RULES
      TRACE_MICROARCHITECTURAL_EXECUTION
      TRACE_PIPELINE_STATE
      TRACE_REGISTER_RENAMING
      ANALYSE_SCHEDULING
      ANALYSE_SPECULATION
      ANALYSE_BRANCH_PREDICTION
      ANALYSE_CACHE_BEHAVIOUR
      ANALYSE_PERFORMANCE
      ANALYSE_POWER_AND_THERMAL_BEHAVIOUR
      CHECK_SEMANTIC_EQUIVALENCE
      PRESERVE_UNCERTAINTY
      TRACE_EVIDENCE
      TRACE_PROVENANCE
      GENERATE_EXPLANATION_PATH
    }

    RESPONSE_POLICY {
      DISTINGUISH_ISA_FROM_MICROARCHITECTURE
      DISTINGUISH_ARCHITECTURAL_FROM_PHYSICAL_REGISTERS
      DISTINGUISH_MACHINE_INSTRUCTIONS_FROM_MICRO_OPERATIONS
      DISTINGUISH_SPECULATIVE_FROM_COMMITTED_STATE
      PRESERVE_WORKLOAD_AND_CONFIGURATION_CONTEXT
      RETURN_CONFIDENCE_WHEN_AVAILABLE
      RETURN_PROVENANCE_WHEN_AVAILABLE
      AVOID_UNSUPPORTED_MICROARCHITECTURAL_INFERENCE
    }
  }

  TERMINAL {
    RESULT =
      VALIDATED(
        SEMANTICALLY_NORMALISED(
          EVIDENCE_LINKED(
            CONFIDENCE_AWARE(
              MICROARCHITECTURE_KNOWLEDGE
            )
          )
        )
      )
  }
}

END FLOW